Application programming interface to indicate parallel scheduling maximum

ABSTRACT

Apparatuses, systems, and techniques to execute CUDA programs. In at least one embodiment, an application programming interface is performed to indicate a maximum number of blocks of threads capable of being scheduled in parallel.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of Indian Provisional ApplicationNo. 202241043444, filed Jul. 29, 2022, entitled “APPLICATION PROGRAMMINGINTERFACES FOR THREAD BLOCKS,” the disclosure of which is incorporatedherein by reference.

This application incorporates by reference for all purposes the fulldisclosures of co-pending U.S. patent application Ser. No. ______, filedconcurrently herewith, entitled “APPLICATION PROGRAMMING INTERFACE TOINDICATE THREAD BLOCKS” (Attorney Docket No. 0112912-497U50), co-pendingU.S. patent application Ser. No. ______, filed concurrently herewith,entitled “APPLICATION PROGRAMMING INTERFACE TO SCHEDULE THREAD BLOCKS”(Attorney Docket No. 0112912-497US1), co-pending U.S. patent applicationSer. No. ______, filed concurrently herewith, entitled “APPLICATIONPROGRAMMING INTERFACE TO PERFORM A SCHEDULING POLICY” (Attorney DocketNo. 0112912-497US2), co-pending U.S. patent application Ser. No. ______,filed concurrently herewith, entitled “APPLICATION PROGRAMMING INTERFACETO INDICATE SCHEDULING POLICIES” (Attorney Docket No. 0112912-497US3),co-pending U.S. patent application Ser. No. ______, filed concurrentlyherewith, entitled “APPLICATION PROGRAMMING INTERFACE TO INDICATEATTRIBUTES OF GROUPS OF BLOCKS OF THREADS” (Attorney Docket No.0112912-497US5), co-pending U.S. patent application Ser. No. ______,filed concurrently herewith, entitled “APPLICATION PROGRAMMING INTERFACETO INDICATE BLOCK MAXIMUM” (Attorney Docket No. 0112912-497US6),co-pending U.S. patent application Ser. No. ______, filed concurrentlyherewith, entitled “APPLICATION PROGRAMMING INTERFACE TO GENERATEKERNELS” (Attorney Docket No. 0112912-497US7), co-pending U.S. patentapplication Ser. No. ______, filed concurrently herewith, entitled“APPLICATION PROGRAMMING INTERFACE TO INDICATE ATTRIBUTE LIMITATIONS”(Attorney Docket No. 0112912-497US8), co-pending U.S. patent applicationSer. No. ______, filed concurrently herewith, entitled “APPLICATIONPROGRAMMING INTERFACE TO INDICATE PERFORMANCE OF BARRIER INSTRUCTION”(Attorney Docket No. 0112912-497US9), co-pending U.S. patent applicationSer. No. ______, filed concurrently herewith, entitled “APPLICATIONPROGRAMMING INTERFACE TO STOP PERFORMANCE OF THREADS” (Attorney DocketNo. 0112912-497USA), co-pending U.S. patent application Ser. No. ______,filed concurrently herewith, entitled “APPLICATION PROGRAMMING INTERFACETO INDICATE PERFORMANCE OF BARRIER INSTRUCTION AND STOP PERFORMANCE OFTHREADS” (Attorney Docket No. 0112912-497USB), and co-pending U.S.patent application Ser. No. ______, filed concurrently herewith,entitled “APPLICATION PROGRAMMING INTERFACE TO SHARE MEMORY BETWEENGROUPS OF BLOCKS OF THREADS” (Attorney Docket No. 0112912-497USC).

FIELD

At least one embodiment pertains to processing resources used to executeone or more CUDA programs. For example, at least one embodiment pertainsto processing resources used to execute one or more CUDA programs thatset parameters of one or more clusters of one or more groups ofinstructions, get parameters of one or more clusters of one or moregroups of instructions, share resources between one or more clusters ofone or more groups of instructions, and/or synchronize execution betweenone or more clusters of one or more groups of instructions.

BACKGROUND

Performing computational operations can use significant memory, time, orcomputing resources. Computer programs can be organized in differentways without various portions that can be performed independently ordependently from one another. Despite computer hardware advances thataccelerate or otherwise assist the performance of the various componentsof a computer program, the advances are generally unable to take intoaccount all the various ways in which computer programs can bestructured. A processor may, for example, be unable to take into accountvarious aspects of a computer program, thereby causing delay or otherinefficiencies.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates an example computer system where software kernels arelaunched using block clusters, in accordance with at least oneembodiment;

FIG. 2 illustrates an example diagram of a thread block where executionthreads are organized, in accordance with at least one embodiment;

FIG. 3 illustrates an example diagram of a compute unit where threadblocks are processed by, in accordance with at least one embodiment;

FIG. 4 illustrates an example diagram of a compute unit where threads ofa thread block are processed, in accordance with at least oneembodiment;

FIG. 5 illustrates an example diagram of a compute unit where blockclusters are processed, in accordance with at least one embodiment;

FIG. 6 illustrates an example process to launch software kernels usingblock clusters, in accordance with at least one embodiment;

FIG. 7 illustrates an example diagram where sizes and dimensions ofblock clusters are shown, in accordance with at least one embodiment;

FIG. 8 illustrates an example application programming interface toindicate dimensions of a block cluster, in accordance with at least oneembodiment;

FIG. 9 illustrates an example application programming interface toobtain dimensions of a block cluster, in accordance with at least oneembodiment;

FIG. 10 illustrates an example diagram where a spread scheduling policyof block clusters is shown, in accordance with at least one embodiment;

FIG. 11 illustrates an example diagram where a balance scheduling policyof block clusters is shown, in accordance with at least one embodiment;

FIG. 12 illustrates an example application programming interface toindicate a scheduling policy of a block cluster, in accordance with atleast one embodiment;

FIG. 13 illustrates an example application programming interface toobtain a scheduling policy of a block cluster, in accordance with atleast one embodiment;

FIG. 14 illustrates an example computer system where a maximum number ofclusters supported by hardware is obtained, in accordance with at leastone embodiment;

FIG. 15 illustrates an example application programming interface toobtain a maximum number of clusters supported by hardware, in accordancewith at least one embodiment;

FIG. 16 illustrates an example diagram where block cluster attributesare indicated and obtained, in accordance with at least one embodiment;

FIG. 17 illustrates an example application programming interface toindicate and obtain attributes of block clusters, in accordance with atleast one embodiment;

FIG. 18 illustrates an example computer system where a maximum clustersize that can be simultaneously performed is obtained, in accordancewith at least one embodiment;

FIG. 19 illustrates an example application programming interface toobtain a maximum cluster size that can be simultaneously performed byhardware, in accordance with at least one embodiment;

FIG. 20 illustrates an example computer system where a software kernelis executed using block clusters, in accordance with at least oneembodiment;

FIG. 21 illustrates an example application programming interface toexecute a software kernel using block clusters, in accordance with atleast one embodiment;

FIG. 22 illustrates an example diagram where a hierarchy of threads,thread blocks, block clusters, compute units, and graphics processors isshown, in accordance with at least one embodiment;

FIG. 23 illustrates an example diagram where thread attributes of acalling thread are obtained, in accordance with at least one embodiment;

FIG. 24 illustrates an example diagram where block cluster attributes ofa calling thread are obtained, in accordance with at least oneembodiment;

FIG. 25 illustrates an example diagram where block cluster groupattributes of a calling thread are obtained, in accordance with at leastone embodiment;

FIG. 26 illustrates an example application programming interface toobtain thread, thread block, block cluster, and block cluster groupattributes of a calling thread, in accordance with at least oneembodiment;

FIG. 27 illustrates an example diagram where threads of a block clusterare waiting on other threads to perform a barrier instruction, inaccordance with at least one embodiment;

FIG. 28 illustrates an example diagram where threads of a block clusterhave performed a barrier instruction, in accordance with at least oneembodiment;

FIG. 29 illustrates an example diagram where threads of a block clusterresume after performing a barrier instruction, in accordance with atleast one embodiment;

FIG. 30 illustrates an example application programming interface todetermine if threads of a block cluster have performed a barrierinstruction, in accordance with at least one embodiment;

FIG. 31 illustrates an example application programming interface todetermine if a thread should stop until all other threads of a blockcluster have performed a barrier instruction, in accordance with atleast one embodiment;

FIG. 32 illustrates an example application programming interface todetermine if threads of a block cluster have performed a barrierinstruction and to stop until all other threads of a block cluster haveperformed a barrier instruction, in accordance with at least oneembodiment;

FIG. 33 illustrates an example diagram where shared memory of a computeunit is mapped between threads of a block cluster, in accordance with atleast one embodiment;

FIG. 34 illustrates an example application programming interface to mapmemory between threads of a block cluster, in accordance with at leastone embodiment;

FIG. 35 illustrates an example software stack where applicationprogramming interface calls associated with block clusters areprocessed, in accordance with at least one embodiment;

FIG. 36 illustrates an exemplary data center, in accordance with atleast one embodiment;

FIG. 37 illustrates a processing system, in accordance with at least oneembodiment;

FIG. 38 illustrates a computer system, in accordance with at least oneembodiment;

FIG. 39 illustrates a system, in accordance with at least oneembodiment;

FIG. 40 illustrates an exemplary integrated circuit, in accordance withat least one embodiment;

FIG. 41 illustrates a computing system, according to at least oneembodiment;

FIG. 42 illustrates an APU, in accordance with at least one embodiment;

FIG. 43 illustrates a CPU, in accordance with at least one embodiment;

FIG. 44 illustrates an exemplary accelerator integration slice, inaccordance with at least one embodiment;

FIGS. 45A and 45B illustrate exemplary graphics processors, inaccordance with at least one embodiment;

FIG. 46A illustrates a graphics core, in accordance with at least oneembodiment;

FIG. 46B illustrates a GPGPU, in accordance with at least oneembodiment;

FIG. 47A illustrates a parallel processor, in accordance with at leastone embodiment;

FIG. 47B illustrates a processing cluster, in accordance with at leastone embodiment;

FIG. 47C illustrates a graphics multiprocessor, in accordance with atleast one embodiment;

FIG. 48 illustrates a graphics processor, in accordance with at leastone embodiment;

FIG. 49 illustrates a processor, in accordance with at least oneembodiment;

FIG. 50 illustrates a processor, in accordance with at least oneembodiment;

FIG. 51 illustrates a graphics processor core, in accordance with atleast one embodiment;

FIG. 52 illustrates a PPU, in accordance with at least one embodiment;

FIG. 53 illustrates a GPC, in accordance with at least one embodiment;

FIG. 54 illustrates a streaming multiprocessor, in accordance with atleast one embodiment;

FIG. 55 illustrates a software stack of a programming platform, inaccordance with at least one embodiment;

FIG. 56 illustrates a CUDA implementation of a software stack of FIG. 55, in accordance with at least one embodiment;

FIG. 57 illustrates a ROCm implementation of a software stack of FIG. 55, in accordance with at least one embodiment;

FIG. 58 illustrates an OpenCL implementation of a software stack of FIG.55 , in accordance with at least one embodiment;

FIG. 59 illustrates software that is supported by a programmingplatform, in accordance with at least one embodiment;

FIG. 60 illustrates compiling code to execute on programming platformsof FIGS. 55-58 , in accordance with at least one embodiment;

FIG. 61 illustrates in greater detail compiling code to execute onprogramming platforms of FIGS. 55-58 , in accordance with at least oneembodiment;

FIG. 62 illustrates translating source code prior to compiling sourcecode, in accordance with at least one embodiment;

FIG. 63A illustrates a system configured to compile and execute CUDAsource code using different types of processing units, in accordancewith at least one embodiment;

FIG. 63B illustrates a system configured to compile and execute CUDAsource code of FIG. 63A using a CPU and a CUDA-enabled GPU, inaccordance with at least one embodiment;

FIG. 63C illustrates a system configured to compile and execute CUDAsource code of FIG. 63A using a CPU and a non-CUDA-enabled GPU, inaccordance with at least one embodiment;

FIG. 64 illustrates an exemplary kernel translated by CUDA-to-HIPtranslation tool of FIG. 63C, in accordance with at least oneembodiment;

FIG. 65 illustrates non-CUDA-enabled GPU of FIG. 63C in greater detail,in accordance with at least one embodiment;

FIG. 66 illustrates how threads of an exemplary CUDA grid are mapped todifferent compute units of FIG. 65 , in accordance with at least oneembodiment; and

FIG. 67 illustrates how to migrate existing CUDA code to Data ParallelC++ code, in accordance with at least one embodiment.

DETAILED DESCRIPTION

FIG. 1 illustrates an example computer system 100 where software kernelsare launched using block clusters, in accordance with at least oneembodiment. In at least one embodiment, a processor 102 executes orotherwise performs one or more commands to generate a software kernel104 and to launch a software kernel 106. In at least one embodiment,processor 102 is a single-core processor, a multi-core processor, agraphics processors, a parallel processor, a general purpose graphicsprocessor, and/or some other processor such as those described herein inconnection with FIGS. 36 to 67 .

In at least one embodiment, software kernel comprises a set of one ormore executable functions, as described herein. In at least oneembodiment, a software kernel is generated (e.g., when processor 102executes or otherwise performs one or more commands to generate asoftware kernel 104) from one or more functions as described herein atleast in connection with FIGS. 63A, 63C, and 64 . In at least oneembodiment, a software kernel is launched (e.g., when processor 102executes or otherwise performs one or more commands to launch a softwarekernel 106 using systems and methods such as those described herein atleast in connection with FIGS. 63A, 63C, and 64 . In at least oneembodiment, a software kernel is referred to as a kernel when, forexample, a kernel is being generated and launched on graphics processorhardware such as that described herein. In at least one embodiment, notshown in FIG. 1 , one or more additional processors may be elements ofexample computer system 100.

In at least one embodiment, processor 102 executes or otherwise performsone or more commands to launch software kernel 106 by causing a softwarekernel to be executed using a graphics processor 108. In at least oneembodiment, graphics processor 108 is a single-core graphics processor,a multi-core graphics processor, a parallel processor, a general purposegraphics processor, and/or some other graphics processor such as thosedescribed herein in connection with FIGS. 45A to 54 . In at least oneembodiment, not shown in FIG. 1 , one or more additional graphicsprocessors may be elements of example computer system 100.

In at least one embodiment, graphics processor 108 includes one or morecompute units (e.g., compute unit 110 and/or compute unit 122). In atleast one embodiment, compute unit 110 (and/or compute unit 122) is acompute unit such as those described herein at least in connection withFIG. 66 . In at least one embodiment, compute unit 110 (and/or computeunit 122) is a programmable streaming multiprocessor (“SM”) 5314 asdescribed herein at least in connection with FIG. 53 . In at least oneembodiment, compute unit 110 (and/or compute unit 122) is a streamingmultiprocessor (“SM”) 5400 as described herein at least in connectionwith FIG. 54 .

In at least one embodiment, compute unit 110 implements one or moreblock clusters such as those described herein (e.g., block cluster 112,block cluster 120, and/or block cluster 118) using systems and methodssuch as those described herein. In at least one embodiment, processor102 executes or otherwise performs one or more commands to launchsoftware kernel 106 by causing a software kernel to be executed usingblock cluster 112 of compute unit 110 on graphics processor 108. In atleast one embodiment, compute unit 110 may include one or moreadditional block clusters such as block cluster 120 that may be used tolaunch one or more other software kernels by a processor such asprocessor 102 and/or by another processor not shown in FIG. 1 . In atleast one embodiment, block cluster 120 may be used to launch one ormore other software kernels before, during, or after processor 102executes or otherwise performs one or more commands to launch softwarekernel 106 using block cluster 112. In at least one embodiment, notshown in FIG. 1 , block cluster 120 may be on a different compute unit(e.g., compute unit 122) than block cluster 112. In at least oneembodiment, not shown in FIG. 1 , block clusters such as block cluster112, block cluster 118, and/or block cluster 120 include one or morethread blocks such as thread block 202, as described herein at least inconnection with FIG. 2 .

In at least one embodiment, processor 102 may also execute or otherwiseperform one or more commands to generate another software kernel 114 andto launch another software kernel 116. In at least one embodiment,software kernel 114 is identical to software kernel 104. In at least oneembodiment, software kernel 114 is different from software kernel 104.In at least one embodiment, processor 102 executes or otherwise performsone or more commands to launch software kernel 116 by causing a softwarekernel to be executed using block cluster 118 of compute unit 110 ongraphics processor 108. In at least one embodiment, block cluster 118may be used to launch software kernel 116 before, during, or afterprocessor 102 executes or otherwise performs one or more commands tolaunch software kernel 106 using block cluster 112. In at least oneembodiment, not shown in FIG. 1 , block cluster 118 may be on adifferent compute unit (e.g., compute unit 122) than block cluster 112.

In at least one embodiment, not shown in FIG. 1 , processor 102 executesor otherwise performs one or more commands to launch software kernel 106by causing a software kernel to be executed using a plurality of blockclusters such as block cluster 112, on a plurality of compute unitsusing a graphics processor 108. In at least one embodiment, for example,processor 102 executes or otherwise performs one or more commands tolaunch software kernel 106 by launching a portion of a software kernelon a block cluster 112 on compute unit 110 and by launching a secondportion of a software kernel on a block cluster (not illustrated in FIG.1 ) on compute unit 122.

In at least one embodiment, processor 102 and/or graphics processor 108comprise one or more circuits to perform an API to indicate two or moreblocks of threads to be scheduled in parallel. In at least oneembodiment, processor 102 and/or graphics processor 108 comprise one ormore circuits to perform an API to indicate one or more dimensions ofone or more clusters of one or more groups of instructions. In at leastone embodiment, processor 102 and/or graphics processor 108 comprise oneor more circuits to perform an API to indicate two or more blocks ofthreads to be scheduled in parallel using an API such as set blockcluster dimension API 802, described herein at least in connection withFIG. 8 . In at least one embodiment, processor 102 and/or graphicsprocessor 108 comprise one or more circuits to perform an API toindicate one or more dimensions of one or more clusters of one or moregroups of instructions using an API such as set block cluster dimensionAPI 802, described herein at least in connection with FIG. 8 .

In at least one embodiment, processor 102 and/or graphics processor 108comprise one or more circuits to perform an API to determine which oftwo or more blocks of threads to be scheduled in parallel. In at leastone embodiment, processor 102 and/or graphics processor 108 comprise oneor more circuits to perform an API to obtain one or more dimensions of aone or more clusters of one or more groups of instructions. In at leastone embodiment, processor 102 and/or graphics processor 108 comprise oneor more circuits to perform an API to determine which of two or moreblocks of threads to be scheduled in parallel using an API such as getcluster dimension API 902, described herein at least in connection withFIG. 9 . In at least one embodiment, processor 102 and/or graphicsprocessor 108 comprise one or more circuits to perform an API to obtainone or more dimensions of a one or more clusters of one or more groupsof instructions using an API such as get cluster dimension API 902,described herein at least in connection with FIG. 9 .

In at least one embodiment, processor 102 and/or graphics processor 108comprise one or more circuits to perform an API comprising one or moreparameters to cause a scheduling policy of one or more blocks of one ormore threads to be performed. In at least one embodiment, processor 102and/or graphics processor 108 comprise one or more circuits to performan API to indicate a scheduling policy of one or more clusters of one ormore groups of instructions. In at least one embodiment, processor 102and/or graphics processor 108 comprise one or more circuits to performan API to comprising one or more parameters to cause a scheduling policyof one or more blocks of one or more threads to be performed using anAPI such as set scheduling policy API 1202, described herein at least inconnection with FIG. 12 . In at least one embodiment, processor 102and/or graphics processor 108 comprise one or more circuits to performan API to indicate a scheduling policy of one or more clusters of one ormore groups of instructions using an API such set scheduling policy API1202, described herein at least in connection with FIG. 12 .

In at least one embodiment, processor 102 and/or graphics processor 108comprise one or more circuits to perform an API comprising one or moreparameters to indicate a scheduling policy of one or more blocks of oneor more threads. In at least one embodiment, processor 102 and/orgraphics processor 108 comprise one or more circuits to perform an APIto obtain a scheduling policy of one or more clusters of one or moregroups of instructions. In at least one embodiment, processor 102 and/orgraphics processor 108 comprise one or more circuits to perform an APIcomprising one or more parameters to indicate a scheduling policy of oneor more blocks of one or more threads using an API such as getscheduling policy API 1302, described herein at least in connection withFIG. 13 . In at least one embodiment, processor 102 and/or graphicsprocessor 108 comprise one or more circuits to perform an API to obtaina scheduling policy of one or more clusters of one or more groups ofinstructions using an API such as get scheduling policy API 1302,described herein at least in connection with FIG. 13 .

In at least one embodiment, processor 102 and/or graphics processor 108comprise one or more circuits to perform an API to indicate a maximumnumber of blocks of threads capable of being scheduled in parallel. Inat least one embodiment, processor 102 and/or graphics processor 108comprise one or more circuits to perform an API to obtain a limit of anumber of allowable clusters of one or more groups of instructions. Inat least one embodiment, processor 102 and/or graphics processor 108comprise one or more circuits to perform an API to indicate a maximumnumber of blocks of threads capable of being scheduled in parallel usingan API such as number of blocks supported API 1502, described herein atleast in connection with FIG. 15 . In at least one embodiment, processor102 and/or graphics processor 108 comprise one or more circuits toperform an API to obtain a limit of a number of allowable clusters ofone or more groups of instructions using an API such as number of blockssupported API 1502, described herein at least in connection with FIG. 15.

In at least one embodiment, processor 102 and/or graphics processor 108comprise one or more circuits to perform an API comprising one or moreparameters to indicate one or more attributes of one or more groups ofblocks of one or more threads. In at least one embodiment, processor 102and/or graphics processor 108 comprise one or more circuits to performan API to obtain one or more attributes of one or more clusters of oneor more groups of instructions. In at least one embodiment, processor102 and/or graphics processor 108 comprise one or more circuits toperform an API comprising one or more parameters to indicate one or moreattributes of one or more groups of blocks of one or more threads usingan API such as indicate cluster parameters API 1702, described herein atleast in connection with FIG. 17 . In at least one embodiment, processor102 and/or graphics processor 108 comprise one or more circuits toperform an API to obtain one or more attributes of one or more clustersof one or more groups of instructions using an API such as indicatecluster parameters API 1702, described herein at least in connectionwith FIG. 17 .

In at least one embodiment, processor 102 and/or graphics processor 108comprise one or more circuits to perform an API to indicate a maximumnumber of blocks of threads to be scheduled in parallel. In at least oneembodiment, processor 102 and/or graphics processor 108 comprise one ormore circuits to perform an API to obtain a limit of a number ofconcurrently performable clusters of one or more groups of instructions.In at least one embodiment, processor 102 and/or graphics processor 108comprise one or more circuits to perform an API to indicate a maximumnumber of blocks of threads to be scheduled in parallel using an APIsuch as maximum cluster size supported API 1902, described herein atleast in connection with FIG. 19 . In at least one embodiment, processor102 and/or graphics processor 108 comprise one or more circuits toperform an API to obtain a limit of a number of concurrently performableclusters of one or more groups of instructions using an API such asmaximum cluster size supported API 1902, described herein at least inconnection with FIG. 19 .

In at least one embodiment, processor 102 and/or graphics processor 108comprise one or more circuits to perform an API to cause a kernel to begenerated to cause two or more blocks of two or more threads to bescheduled in parallel. In at least one embodiment, processor 102 and/orgraphics processor 108 comprise one or more circuits to perform an APIto cause a software kernel to be performed using one or more clusters ofone or more groups of instructions. In at least one embodiment,processor 102 and/or graphics processor 108 comprise one or morecircuits to perform an API to cause a kernel to be generated to causetwo or more blocks of two or more threads to be scheduled in parallelusing an API such as launch kernel with block clusters API 2102,described herein at least in connection with FIG. 21 . In at least oneembodiment, processor 102 and/or graphics processor 108 comprise one ormore circuits to perform an API to cause a software kernel to beperformed using one or more clusters of one or more groups ofinstructions using an API such as launch kernel with block clusters API2102, described herein at least in connection with FIG. 21 .

In at least one embodiment, processor 102 and/or graphics processor 108comprise one or more circuits to perform an API comprising one or moreparameters to indicate one or more limitations of one or more attributesof one or more groups of blocks of one or more threads. In at least oneembodiment, processor 102 and/or graphics processor 108 comprise one ormore circuits to perform an API to obtain one or more parameters of oneor more clusters of one or more groups of instructions of a set of oneor more clusters of one or more groups of instructions. In at least oneembodiment, processor 102 and/or graphics processor 108 comprise one ormore circuits to perform an API comprising one or more parameters toindicate one or more limitations of one or more attributes of one ormore groups of blocks of one or more threads using an API such as getattributes API 2602, described herein at least in connection with FIG.26 . In at least one embodiment, processor 102 and/or graphics processor108 comprise one or more circuits to perform an API to obtain one ormore parameters of one or more clusters of one or more groups ofinstructions of a set of one or more clusters of one or more groups ofinstructions using an API such as get attributes API 2602, describedherein at least in connection with FIG. 26 .

In at least one embodiment, processor 102 and/or graphics processor 108comprise one or more circuits to perform an API to indicate whether oneor more threads within two or more blocks of threads have performed abarrier instruction. In at least one embodiment, processor 102 and/orgraphics processor 108 comprise one or more circuits to perform an APIindicate arrival at a barrier instruction of a cluster of one or moregroups of instructions. In at least one embodiment, processor 102 and/orgraphics processor 108 comprise one or more circuits to perform an APIto indicate whether one or more threads within two or more blocks ofthreads have performed a barrier instruction using an API such as kernelbarrier arrive API 3002, described herein at least in connection withFIG. 30 . In at least one embodiment, processor 102 and/or graphicsprocessor 108 comprise one or more circuits to perform an API toindicate arrival at a barrier instruction of a cluster of one or moregroups of instructions using an API such as kernel barrier arrive API3002, described herein at least in connection with FIG. 30 .

In at least one embodiment, processor 102 and/or graphics processor 108comprise one or more circuits to perform an API to cause performance ofone or more threads within a group of blocks of threads to stop at leastuntil all threads within the group of blocks have performed a barrierinstruction. In at least one embodiment, processor 102 and/or graphicsprocessor 108 comprise one or more circuits to perform an API to causeone or more first instructions to be prevented from being performeduntil a cluster of one or more groups of instructions have performed oneor more second instructions. In at least one embodiment, processor 102and/or graphics processor 108 comprise one or more circuits to performan API to cause performance of one or more threads within a group ofblocks of threads to stop at least until all threads within the group ofblocks have performed a barrier instruction using an API such as kernelbarrier wait API 3102, described herein at least in connection with FIG.31 . In at least one embodiment, processor 102 and/or graphics processor108 comprise one or more circuits to perform an API to cause one or morefirst instructions to be prevented from being performed until a clusterof one or more groups of instructions have performed one or more secondinstructions using an API such as kernel barrier wait API 3102,described herein at least in connection with FIG. 31 .

In at least one embodiment, processor 102 and/or graphics processor 108comprise one or more circuits to perform an API to indicate whether oneor more threads within two or more blocks of threads have performed abarrier instruction and to cause performance of one or more threadswithin the group of blocks of threads to stop at least until all threadswithin the group of blocks have performed the barrier instruction. In atleast one embodiment, processor 102 and/or graphics processor 108comprise one or more circuits to perform an API to indicate whether oneor more threads within two or more blocks of threads have performed abarrier instruction and to cause performance of one or more threadswithin the group of blocks of threads to stop at least until all threadswithin the group of blocks have performed the barrier instruction usingan API such as a kernel barrier sync API 3202, described herein at leastin connection with FIG. 32 . In at least one embodiment, processor 102and/or graphics processor 108 comprise one or more circuits to performan API to cause one or more first instructions to be prevented frombeing performed until a cluster of one or more groups of instructionshave performed one or more second instructions using an API such as akernel barrier sync API 3202, described herein at least in connectionwith FIG. 32 .

In at least one embodiment, processor 102 and/or graphics processor 108comprise one or more circuits to perform an API to cause memory to beshared between two or more groups of blocks of thread. In at least oneembodiment, processor 102 and/or graphics processor 108 comprise one ormore circuits to perform an API to cause one or more memory locations offirst cluster of one or more groups of instructions to be accessible toa second cluster of one or more groups of instructions. In at least oneembodiment, processor 102 and/or graphics processor 108 comprise one ormore circuits to perform an API to cause memory to be shared between twoor more groups of blocks of thread using an API such as map sharedmemory API 3402, described herein at least in connection with FIG. 34 .In at least one embodiment, processor 102 and/or graphics processor 108comprise one or more circuits to perform an API to cause one or morememory locations of first cluster of one or more groups of instructionsto be accessible to a second cluster of one or more groups ofinstructions using an API such as map shared memory API 3402, describedherein at least in connection with FIG. 34 .

FIG. 2 illustrates an example diagram 200 of a thread block 202 whereexecution threads are organized, in accordance with at least oneembodiment. In at least one embodiment, thread block 202 includes one ormore threads. In at least one embodiment, thread block 202 is athree-dimensional (3D) thread block that has dimensions (T_(x), T_(y),T_(z)) (e.g., there are T_(x)×T_(y)×T_(z) threads). In at least oneembodiment, for example, if T_(x) is 8, T_(y) is 8, and T_(z) is 4,thread block 202 includes 256 threads. In at least one embodiment,thread block 202 may be one-dimensional (e.g., may have T_(x) threads),or may be two-dimensional (e.g., may have T_(x)×T_(y) threads), may befour-dimensional (e.g., may have T_(x)×T_(y)×T_(z)×T_(w) threads), ormay have some other dimensionality. In at least one embodiment, threadblock 202 is a thread block such as thread blocks 6630(1,1)-6630(BX,BY),described herein at least in connection with FIG. 66 .

In at least one embodiment, thread block 202 includes a plurality ofthreads in a grid (e.g., a T_(x)×T_(y)×T_(z) grid) which are threadssuch as threads 6640(1,1)-6640(TX,TY) as described herein at least inconnection with FIG. 66 . In at least one embodiment, threads of threadblock 202 may be used to execute a software kernel such those described.In at least one embodiment, for example, threads of thread block 202 maybe used to execute a software kernel when processor 102 launches kernel106 using block cluster 112, as described herein at least in connectionwith FIG. 1 .

FIG. 3 illustrates an example diagram 300 of a compute unit 302 wherethread blocks are processed, in accordance with at least one embodiment.In at least one embodiment, compute unit 302 is a compute unit such ascompute unit 110 and/or compute unit 122, as described herein at leastin connection with FIG. 1 . In at least one embodiment, compute unit 302has one or more thread blocks such as thread block 202, as describedherein at least in connection with FIG. 2 . In at least one embodiment,compute unit 302 includes shared memory 304, which is shared memory suchas shared memory 6660(1) and/or shared memory 6660(2), as describedherein at least in connection with FIG. 66 . In at least one embodiment,shared memory 304 comprises one or more memory locations accessible byone or more threads, one or more thread blocks, and/or one or more blockclusters. In at least one embodiment, shared memory 304 includes one ormore physical memory locations. In at least one embodiment, sharedmemory 304 includes one or more virtual memory locations. In at leastone embodiment, shared memory 304 is memory hosted by a processor and/ora graphics processing unit (GPU) such as those described herein.

In at least one embodiment, not shown in FIG. 3 , blocks (e.g., threadblocks) are executed using an entire graphics processor such as graphicsprocessor 108, described herein at least in connection with FIG. 1 ,with one or more blocks (e.g., thread blocks) executing on each of aplurality of compute units such as compute unit 302. In at least oneembodiment, blocks of a grid of blocks as illustrated in FIG. 3 areorganized as a logical grid so that, for example, block (1,1,1) may behosted on a first compute unit and a logically neighboring block (e.g.,block (1,1,2), block (1,2,1), block (2,1,1), etc.) may be on a differentcompute unit.

In at least one embodiment, compute unit 302 has a three-dimensional(3D) grid of thread block that has dimensions (B_(x), B_(y), B_(z))(e.g., there are B_(x)×B_(y)×B_(z) thread blocks). In at least oneembodiment, for example, if B_(x) is 4, B_(y) is 4, and B_(z) is 4,compute unit 302 includes 64 thread blocks. In at least one embodiment,where, for example, a thread block has 256 threads, compute unit 302 mayhave 16,384 threads. In at least one embodiment, compute unit 302 may beone-dimensional (e.g., may have B_(x) thread blocks), or may betwo-dimensional (e.g., may have B_(x)×B_(y) thread blocks), may befour-dimensional (e.g., may have B_(x)×B_(y)×B_(z)×B_(w) thread blocks),or may have some other dimensionality. In at least one embodiment,thread blocks of compute unit 302 are used to execute a software kernelsuch those described. In at least one embodiment, for example, threadblocks of compute unit 302 are used to execute a software kernel whenprocessor 102 launches kernel 106 using block cluster 112, as describedherein at least in connection with FIG. 1 .

FIG. 4 illustrates an example diagram 400 of a compute unit 402 wherethreads of a thread block are processed, in accordance with at least oneembodiment. In example computer system 400 illustrated in FIG. 4 ,thread blocks 406 are illustrated in two dimensions for clarity (e.g., aB_(z) dimension of a compute unit 402 is 1). In at least one embodiment,compute unit 402 is a compute unit such as those described herein. In atleast one embodiment, compute unit 402 is referred to as a grid. In atleast one embodiment, compute unit 402 includes shared memory 404 andone or more thread blocks 406. In at least one embodiment, thread blocks406 are contained in one or more block clusters, as described herein. Inat least one embodiment, thread blocks 406 of compute unit 402 are usedto execute a software kernel such those described. In at least oneembodiment, for example, thread blocks 406 of compute unit 402 are usedto execute a software kernel when processor 102 launches kernel 106using block cluster 112, as described herein at least in connection withFIG. 1 .

In at least one embodiment, not shown in FIG. 4 , thread blocks areexecuted using an some or all of a graphics processor such as graphicsprocessor 108, described herein at least in connection with FIG. 1 ,with one or more thread blocks executing on each of a plurality ofcompute units such as compute unit 402, as described herein. In at leastone embodiment, dimensions of thread blocks of a grid of blocks on acompute unit, as illustrated in FIG. 4 , are organized logically asdescribed herein and have different dimensions so that, for example, afirst compute unit may have a grid size of (3,4,1), a second computeunit may have a grid size of (2,2,2), etc.

FIG. 5 illustrates an example diagram 500 of a compute unit 502 whereblock clusters are processed, in accordance with at least oneembodiment. In example computer system 500 illustrated in FIG. 5 ,thread blocks of block clusters 506 are illustrated in two dimensionsfor clarity (e.g., a B_(z) dimension of a compute unit 502 is 1). In atleast one embodiment, compute unit 502 is a compute unit such as thosedescribed herein. In at least one embodiment, compute unit 502 includesshared memory 504 and one or more thread blocks in one or more blockclusters 506.

In at least one embodiment, block clusters 506 includes twelve threadblocks (e.g., a 3×4×1 grid of thread blocks) that are distributed amongsix block clusters (e.g., a 2D 2×3 grid of block clusters). In at leastone embodiment, a block cluster 508 includes four thread blocks. In atleast one embodiment, thread block (1,1) of block cluster 508 is threadblock (1,1,1) of thread blocks 406, thread block (1,2) of block cluster508 is thread block (1,2,1) of thread blocks 406, thread block (2,1) ofblock cluster 508 is thread block (2,1,1) of thread blocks 406, andthread block (2,2) of block cluster 508 is thread block (2,2,1) ofthread blocks 406, described herein at least in connection with FIG. 4 .In at least one embodiment, block cluster 508 has identifier (1,1) andhas dimensions of (2,2).

In at least one embodiment, a block cluster 510 includes two threadblocks. In at least one embodiment, thread block (1,1) of block cluster510 is thread block (1,3,1) of thread blocks 406 and thread block (2,1)of block cluster 510 is thread block (2,3,1) of thread blocks 406,described herein at least in connection with FIG. 4 . In at least oneembodiment, block cluster 510 has identifier (1,2) and has dimensions of(2,1).

In at least one embodiment, a block cluster 512 includes two threadblocks. In at least one embodiment, thread block (1,1) of block cluster512 is thread block (1,4,1) of thread blocks 406 and thread block (2,1)of block cluster 512 is thread block (2,4,1) of thread blocks 406,described herein at least in connection with FIG. 4 . In at least oneembodiment, block cluster 512 has identifier (1,3) and has dimensions of(2,1).

In at least one embodiment, a block cluster 514 includes two threadblocks. In at least one embodiment, thread block (1,1) of block cluster514 is thread block (3,1,1) of thread blocks 406 and thread block (1,2)of block cluster 512 is thread block 3,2,1) of thread blocks 406,described herein at least in connection with FIG. 4 . In at least oneembodiment, block cluster 514 has identifier (2,1) and has dimensions of(1,2).

In at least one embodiment, a block cluster 516 includes one threadblock. In at least one embodiment, thread block (1,1) of block cluster516 is thread block (3,3,1) of thread blocks 406, described herein atleast in connection with FIG. 4 . In at least one embodiment, blockcluster 516 has identifier (2,2) and has dimensions of (1,1). In atleast one embodiment, a block cluster 518 includes one thread block. Inat least one embodiment, thread block (1,1) of block cluster 518 isthread block (3,4,1) of thread blocks 406, described herein at least inconnection with FIG. 4 . In at least one embodiment, block cluster 518has identifier (2,3) and has dimensions of (1,1).

In at least one embodiment, thread blocks of block clusters 506 ofcompute unit 502 are used to execute a software kernel such thosedescribed. In at least one embodiment, for example, thread blocks ofblock clusters 506 of compute unit 402 are used to execute a softwarekernel when processor 102 launches kernel 106 using block cluster 112,as described herein at least in connection with FIG. 1 . In at least oneembodiment, threads, thread blocks, block clusters, and compute units(also referred to herein as grids) are organized and/or indexed asillustrated in FIG. 5 . In at least one embodiment, threads, threadblocks, block clusters, and compute units (also referred to herein asgrids) are organized and/or indexed using some other method including,but not limited to, one or more dynamic methods that may be used todetermine dimensions, indices, and/or identifiers of threads, threadblocks, block clusters, and/or compute units based, at least in part, onGPU architecture, number of compute units of a GPU, number of cores of aGPU, etc. In at least one embodiment, dimensions, indices, and/oridentifiers of threads, thread blocks, block clusters, and/or computeunits are referred to as properties of a group of blocks of threads.

In at least one embodiment, block clusters such as those illustrated inFIG. 5 execute on different compute units (not illustrated in FIG. 5 )so that, for example, block cluster 508 executes on a first computeunit, block cluster 510 executes on a second compute unit, block cluster512 executes on a third compute unit, etc. In at least one embodiment,one or more block clusters execute on a single compute unit and aplurality of block clusters execute on a plurality of compute units. Inat least one embodiment, as described herein, thread blocks if a blockcluster (e.g., block cluster 508) are organized logically so that, forexample, thread block (1,1) executes on a first compute unit, threadblock (1,2) executes on a second compute unit, etc.

In at least one embodiment, a block cluster is a group of thread blockswithin a higher level of a hierarchy that organizes threads, where agroup of thread blocks can be an organizational construct that comprisesone or more thread blocks. In at least one embodiment, a block cluster(which may also be referred to in other ways, such as a cluster) is asubset of a grid of thread blocks. In at least one embodiment, a blockcluster is a partition of a partitioning of a set of thread blocks, suchas a partitioning of a grid of thread blocks or a partitioning of a setof thread blocks that comprise a software kernel. In at least oneembodiment, a block cluster is a subset of a set of thread blocks (e.g.,of a grid or of a software kernel), where a set is organized intosubsets of thread blocks and where subsets can overlap (e.g., have oneor more thread blocks that are common to a plurality of subsets) orwhere subsets are disjoint (e.g., have no thread block that is a memberof multiple subsets). In at least one embodiment, applicationprogramming interfaces (APIs), such as described below and elsewhereherein, which may be CUDA APIs, OneAPI APIs, HIP APIs and/or other APIssuch as described herein, are callable to obtain information about andotherwise manage block clusters and other hierarchical groupings ofthreads, such as grids, thread blocks, warps, and other groupings ofthreads. In at least one embodiment, one or more APIs such as thosedescribed herein are used to manage one or more portions of a blockcluster, using systems and methods such as those described herein. In atleast one embodiment, as used herein, an application programminginterface is referred to as an API.

FIG. 6 illustrates an example process 600 to launch software kernelsusing block clusters, in accordance with at least one embodiment. In atleast one embodiment, a processor such as processor 102 (e.g., a CPU),described herein at least in connection with FIG. 1 , executes orotherwise performs one or more commands to perform example process 600.In at least one embodiment, a graphics processor such as graphicsprocessor 108, described herein at least in connection with FIG. 1 ,executes or otherwise performs one or more commands to perform exampleprocess 600. In at least one embodiment, a processor such as one or moreof those described herein, executes or otherwise performs one or morecommands to perform example process 600.

In at least one embodiment, at step 602 of example process 600, aprocessor performing example process 600 receives a kernelspecification. In at least one embodiment, a kernel specificationreceived at step 602 is an argument of an API such as those describedherein. In at least one embodiment, at step 602, a kernel specificationreceived at step 602 may be used to generate and/or launch a softwarekernel, as described herein. In at least one embodiment, at step 602, akernel specification received at step 602 may be used to generate and/orlaunch a software kernel using one or more block clusters, as describedherein. In at least one embodiment, after step 602, example process 600advances to step 604.

In at least one embodiment, at step 604 of example process 600, aprocessor performing example process 600 receives cluster parameters. Inat least one embodiment, a cluster parameters received at step 604 arearguments of an API such as those described herein. In at least oneembodiment, at step 604, cluster parameters received are clusterparameters that describe one or more aspects of a block clusterincluding, but not limited to, size of one or more block clusters, shapeof one or more block clusters, scheduling policies, executionpriorities, memory management techniques, synchronization methods,and/or other cluster parameters such as those described herein. In atleast one embodiment, at step 604, cluster parameters are received usingone or more application programming interfaces (APIs) such as thosedescribed herein. In at least one embodiment, after step 604, exampleprocess 600 advances to step 606.

In at least one embodiment, at step 606 of example process 600, aprocessor performing example process 600 sets one or more known clusterparameters. In at least one embodiment, at step 606, a processorperforming example process 600 sets one or more known cluster parametersas a result of execution of an API such as those described herein. In atleast one embodiment, at step 606, a processor performing exampleprocess 600 sets one or more known cluster parameters by altering one ormore values in a data structure used to store cluster parameters ofblock clusters. In at least one embodiment, at step 606 a processorperforming example process 600 sets one or more known cluster parametersby calculating parameters, reading parameters from memory, derivingparameters, and/or storing parameters, as described herein. In at leastone embodiment, at step 606, a processor performing example process 600sets one or more default values of cluster parameters where clusterparameters received at step 604 do not include parameters and/or wheredefault values are specified to indicate missing parameters. In at leastone embodiment, at step 606, for example, a block cluster may have adefault size that may be used in an embodiment where one or more knowncluster parameters received at step 606 does not include a sizeparameter. In at least one embodiment, after step 606, example process600 advances to step 608.

In at least one embodiment, at step 608 of example process 600, aprocessor performing example process 600 determines whether otherparameters are needed to complete a specification of a block cluster. Inat least one embodiment, at step 608, some parameters received at step606 may not be specified and, accordingly, other parameters may beneeded to complete a specification of a block cluster. In at least oneembodiment, at step 608, if a processor performing example process 600determines that other parameters are needed to complete a specificationof a block cluster (“YES” branch) example process 600 advances to step610. In at least one embodiment, at step 608, if a processor performingexample process 600 determines that other parameters are not needed tocomplete a specification of a block cluster (“NO” branch) exampleprocess 600 advances to step 612.

In at least one embodiment, at step 610 of example process 600, aprocessor performing example process 600 sets one or more other clusterparameters are set (e.g., parameters not set at step 606), using systemsand methods such as those described herein. In at least one embodiment,at step 610, a processor performing example process 600 sets one or moreother cluster parameters using default parameters, as described herein.In at least one embodiment, at step 610, a processor performing exampleprocess 600 derives one or more other cluster parameters from existingparameters. In at least one embodiment, for example, if dimensionparameters are received at step 604 (e.g., a dimension of X, Y, Z, asdescribed herein), at step 610, a size parameter (e.g., X times Y timeZ) is derived from dimensions. In at least one embodiment, after step610, example process 600 advances to step 612.

In at least one embodiment, at step 612 of example process 600, aprocessor performing example process 600 sets one or more clusterattributes, using systems and methods such as those described herein. Inat least one embodiment, at step 612, a processor performing exampleprocess 600 sets one or more cluster attributes using one or more APIs,such as described herein. In at least one embodiment, at step 612, aprocessor performing example process 600 sets one or more clusterattributes using one or more compile-time APIs, as described herein. Inat least one embodiment, at step 612, a processor performing exampleprocess 600 sets one or more cluster attributes using one or morelaunch-time APIs, as described herein. In at least one embodiment, atstep 612, a processor performing example process 600 sets one or morecluster attributes using one or more run-time APIs, as described herein.In at least one embodiment, after step 612, example process 600 advancesto step 614.

In at least one embodiment, at step 614 of example process 600, aprocessor performing example process 600 determines whether one or morecluster attributes have been set. In at least one embodiment, at step614, if it is determined that one or more cluster attributes have notbeen set (“NO” branch) example process 600 advances to step 616. In atleast one embodiment, at step 614, if it is determined that one or morecluster attributes have been set (“YES” branch) example process 600advances to step 618.

In at least one embodiment, at step 616 of example process 600, aprocessor performing example process 600 returns an error. In at leastone embodiment, a processor performing example process 600 returns anerror as a result of determining that one or more cluster attributeshave not been set (e.g., at step 614). In at least one embodiment, atstep 616, a processor performing example process 600 returns an error toa calling process such as those described herein. In at least oneembodiment, after step 616, example process 600 terminates. In at leastone embodiment, not shown in FIG. 6 , after step 616, example process600 continues at step 602 to receive another kernel specification.

In at least one embodiment, at step 618 of example process 600, aprocessor performing example process 600 launches a kernel using one ormore block clusters using systems and methods such as those describedherein. In at least one embodiment, a processor performing exampleprocess 600 causes some other processor such as those described hereinto launch a kernel using one or more block clusters. In at least oneembodiment, after step 618, example process 600 advances to step 620.

In at least one embodiment, at step 620 of example process 600, aprocessor performing example process 600 returns an indicator ofsuccess. In at least one embodiment, a processor performing exampleprocess 600 returns an indicator of success as a result of determiningthat one or more cluster attributes have been set (e.g., at step 614)and after launching a kernel using a cluster (e.g., at step 618). In atleast one embodiment, at step 620, an indicator of success is returnedto a calling process such as those described herein. In at least oneembodiment, after step 620, example process 600 terminates. In at leastone embodiment, not shown in FIG. 6 , after step 620, example process600 continues at step 602 to receive another kernel specification.

In at least one embodiment, operations of example process 600 areperformed in a different order than is illustrated in FIG. 6 . In atleast one embodiment, operations of example process 600 are performedsimultaneously or in parallel. In at least one embodiment, for example,operations that do not depend on each other (e.g., are orderindependent) are performed simultaneously or in parallel. In at leastone embodiment, operations of example process 600 are performed by aplurality of threads executing on a processor such as those describedherein.

FIG. 7 illustrates an example diagram 700 where sizes and dimensions ofblock clusters are shown, in accordance with at least one embodiment. Inat least one embodiment, an operation to set block cluster size 702 isperformed as described herein (e.g., using set block cluster dimensionAPI 802, described herein at least in connection with FIG. 8 ). In atleast one embodiment, set block cluster size 702 specifies a blockcluster size (e.g., 8). In at least one embodiment, set block clustersize 702 specifies one or more block cluster dimensions (e.g., (2,2,2)or (2,4,1), or (4,2,1), or (8,1,1)), or some other such dimensions. Inat least one embodiment, set block cluster size 702 specifies size butnot dimension. In at least one embodiment, set block cluster size 702specifies dimension but not size. In at least one embodiment, dimensionsare computed from size. In at least one embodiment, size is computedfrom dimensions.

In at least one embodiment, a block cluster 704 with eight blocks thathas dimensions (2,2,2) is created. In at least one embodiment, a blockcluster 706 with eight blocks that has dimensions (2,4,1) is created. Inat least one embodiment, a block cluster 708 with eight blocks that hasdimensions (8,1,1) is created. In at least one embodiment, a blockcluster that has two dimensions is created (e.g., (2,4) or (8,1)). In atleast one embodiment, a block cluster that has one dimension is created(e.g., (8)). In at least one embodiment, a block cluster that has four(or more) dimensions is created (e.g., (2,1,2,2), (2,1,2,1,2), etc.).

FIG. 8 illustrates an example application programming interface 800 toindicate dimensions of a block cluster, in accordance with at least oneembodiment. In at least one embodiment, example application programminginterface 800 for indicating dimensions of a block cluster is a setblock cluster dimension API 802. In at least one embodiment, an API suchas set block cluster dimension API 802 is performed by a processor, suchas those described herein. In at least one embodiment, an API such asset block cluster dimension API 802 is performed as one or more steps ofa computer-implemented method, as described herein. In at least oneembodiment, an API such as set block cluster dimension API 802 isperformed by one or more processors of a computer system, as describedherein. In at least one embodiment, an API such as set block clusterdimension API 802 is stored as instructions on a machine-readablemedium, which can be performed using one or more processors, asdescribed herein. In at least one embodiment, an API such as set blockcluster dimension API 802, when performed, is to indicate two or moreblocks of threads to be scheduled in parallel.

In at least one embodiment, set block cluster dimension API 802 is anAPI to indicate two or more blocks of threads to be scheduled inparallel. In at least one embodiment, set block cluster dimension API802 is an API to indicate one or more dimensions of one or more clustersof one or more groups of instructions. In at least one embodiment, setblock cluster dimension API 802 is an API to set sizes and/or dimensionsof block clusters as described herein at least in connection with FIG. 7. In at least one embodiment, set block cluster dimension API 802receives one or more parameters including, but not limited to, adimension attribute 804, a dimension value 806, and a kernel identifier808. In at least one embodiment, set block cluster dimension API 802returns a return value 818.

In at least one embodiment, dimension attribute 804 of set block clusterdimension API 802 is an attribute that indicates that set block clusterdimension API 802 is setting a dimension value 806. In at least oneembodiment, for example, dimension attribute 804 may be athree-dimensional attribute and dimension value 806 may be three values(e.g., one value corresponding to each of three dimensions). In at leastone embodiment, kernel identifier 808 is an identifier of a kernel thatwill be launched using a block cluster of dimensions specified in setblock cluster dimension API 802 using systems and methods such as thosedescribed herein.

In at least one embodiment, not shown in FIG. 8 , set block clusterdimension API 802 receives one or more additional parameters and/or offlags that specify how dimension attribute 804, dimension value 806,and/or kernel identifier 808 will be used to indicate dimensions of ablock cluster. In at least one embodiment, when additional parametersand/or of flags that specify how dimension attribute 804, dimensionvalue 806, and/or kernel identifier 808 will be used to indicatedimensions of a block cluster are not received, one or more defaultparameters and/or flags may be used by set block cluster dimension API802 to obtain dimensions of a block cluster, using systems and methodssuch as those described herein.

In at least one embodiment, set block cluster dimension API 802 causes aprocessor such as those described herein to execute one or more commandsto verify block cluster dimension attributes and attribute values 810and set block cluster dimensions of a kernel 812, as identified bykernel identifier 808. In at least one embodiment, set block clusterdimension API 802 causes a processor such as those described herein toexecute one or more commands to launch a kernel 814 using a blockcluster as described herein. In at least one embodiment, not shown inFIG. 8 , one or more commands to launch a kernel 814 are executed at adifferent time and/or by a different API.

In at least one embodiment, set block cluster dimension API 802 returnssuccess or failure 816 using return value 818. In at least oneembodiment, set block cluster dimension API 802 returns success usingreturn value 818 when set block cluster dimension API 802 sets blockcluster dimension attributes of a kernel, as described herein. In atleast one embodiment, set block cluster dimension API 802 returnsfailure using return value 818 when set block cluster dimension API 802does not set block cluster dimension attributes of a kernel, asdescribed herein.

In at least one embodiment, set block cluster dimension API 802 returnssuccess or failure 816 using return value 818 to a calling process suchas example process 600 described herein at least in connection with FIG.6 . In at least one embodiment, set block cluster dimension API 802returns success or failure 816 using return value 818 to a callingprocess using integer value, or using a Boolean value, or using anenumerated value, or using a flag, or using a signal, or using asemaphore, or using an event, or using a combination of these and/orother such return value types including, but not limited to, thosedescribed herein.

FIG. 9 illustrates an example application programming interface 900 toobtain dimensions of a block cluster, in accordance with at least oneembodiment. In at least one embodiment, example application programminginterface 900 to obtain dimensions of a block cluster is a get clusterdimension API 902. In at least one embodiment, an API such as getcluster dimension API 902 is performed by a processor, such as thosedescribed herein. In at least one embodiment, an API such as get clusterdimension API 902 is performed as one or more steps of acomputer-implemented method, as described herein. In at least oneembodiment, an API such as get cluster dimension API 902 is performed byone or more processors of a computer system, as described herein. In atleast one embodiment, an API such as get cluster dimension API 902 isstored as instructions on a machine-readable medium, which can beperformed using one or more processors, as described herein. In at leastone embodiment, an API such as get cluster dimension API 902, whenperformed, is to determine which of two or more blocks of threads to bescheduled in parallel.

In at least one embodiment, get cluster dimension API 902 is an API todetermine which of two or more blocks of threads to be scheduled inparallel. In at least one embodiment, get cluster dimension API 902 isan API to obtain one or more dimensions of a one or more clusters of oneor more groups of instructions. In at least one embodiment, get clusterdimension API 902 is an API to is an API to get sizes and/or dimensionsof block clusters as described herein at least in connection with FIG. 7. In at least one embodiment, get cluster dimension API 902 receives oneor more parameters including, but not limited to, a cluster identifier904. In at least one embodiment, get cluster dimension API 902 returns areturn value 912.

In at least one embodiment, cluster identifier 904 of get clusterdimension API 902 is an identifier used to identify a cluster usingsystems and methods such as those described herein. In at least oneembodiment, for example, cluster identifier 904 is an indexed value of acluster that is based on a total number of clusters of a compute unit.In at least one embodiment, cluster identifier 904 is a location of acluster within a group of clusters.

In at least one embodiment, not shown in FIG. 9 , get cluster dimensionAPI 902 receives one or more additional parameters and/or of flags thatspecify how cluster identifier 904 will be used to obtain dimensions ofa block cluster. In at least one embodiment, when additional parametersand/or of flags that specify how cluster identifier 904 will be used toobtain dimensions of a block cluster are not received, one or moredefault parameters and/or flags may be used by get cluster dimension API902 to obtain dimensions of a block cluster, using systems and methodssuch as those described herein.

In at least one embodiment, get cluster dimension API 902 causes aprocessor such as those described herein to execute one or more commandsto determine 906 whether dimensions of a cluster are set, as describedherein. In at least one embodiment, if it is determined that dimensionsare not set (“NO” branch), a default return value 908 may be returned(e.g., (0,0,0)). In at least one embodiment, if it is determined thatdimensions are set (“YES” branch), dimensions of a cluster are returned910. In at least one embodiment, get cluster dimension API 902 returnsdimensions or default values using return value 912.

In at least one embodiment, get cluster dimension API 902 returnsdimensions or default values using return value 912 to a calling processsuch as example process 600 described herein at least in connection withFIG. 6 . In at least one embodiment, get cluster dimension API 902returns dimensions or default values using return value 912 to a callingprocess using integer value, or using a Boolean value, or using anenumerated value, or using a flag, or using a signal, or using asemaphore, or using an event, or using a combination of these and/orother such return value types including, but not limited to, thosedescribed herein.

FIG. 10 illustrates an example diagram 1000 where a spread schedulingpolicy of block clusters is shown, in accordance with at least oneembodiment. In at least one embodiment, a block cluster 1002 with aspread scheduling policy 1004 causes thread blocks to be distributed tomultiple compute units, for example, as many compute units as possible.In at least one embodiment, spread scheduling policy 1004 is set usingset scheduling policy API 1202, described herein at least in connectionwith FIG. 12 . In at least one embodiment, for example, block cluster1002 with spread scheduling policy 1004 distributes four thread blocksto four compute units (e.g., thread block 1006 to compute unit 1014,thread block 1008 to compute unit 1016, thread block 1010 to computeunit 1018, and thread block 1012 to compute unit 1020). In at least oneembodiment, a scheduling policy such as spread scheduling policy 1004 isa preferred scheduling policy so that, for example, when thread blocksare distributed to compute units, a scheduling policy may be satisfiedor may be violated (e.g., multiple thread blocks may be distributed to asingle compute unit). In at least one embodiment, a scheduling policysuch as spread scheduling policy 1004 is a default scheduling policy.

FIG. 11 illustrates an example diagram 1100 where a balance schedulingpolicy of block clusters is shown, in accordance with at least oneembodiment. In at least one embodiment, a block cluster 1102 with abalance scheduling policy 1104 causes thread blocks to be balanced amongavailable compute units so that work loading is evenly distributedbetween compute units. In at least one embodiment, balance schedulingpolicy 1104 is set using set scheduling policy API 1202, describedherein at least in connection with FIG. 12 . In at least one embodiment,for example, thread block 1106 is distributed to compute unit 1114,where compute unit 1114 has thread block 1122 (e.g., from a differentblock cluster, not shown in FIG. 11 ), thread block 1108 and threadblock 1110 are distributed to compute unit 1116, which has no otherthread blocks, thread block 1112 is distributed to compute unit 1120,which has no other thread blocks, and no thread blocks from blockcluster 1102 are distributed to compute unit 1118, because compute unit1118 already has thread block 1124 and thread block 1126 (e.g., from adifferent block cluster not shown in FIG. 11 ). In at least oneembodiment, a scheduling policy such as balance scheduling policy 1104is a preferred scheduling policy so that, for example, when threadblocks are distributed to compute units, a scheduling policy may besatisfied or may be violated (e.g., thread blocks may be distributed tocompute unit in an unbalanced manner). In at least one embodiment, ascheduling policy such as balance scheduling policy 1104 is a defaultscheduling policy.

FIG. 12 illustrates an example application programming interface 1200 toindicate a scheduling policy of a block cluster, in accordance with atleast one embodiment. In at least one embodiment, example applicationprogramming interface 1200 to indicate a scheduling policy of a blockcluster is a set scheduling policy API 1202. In at least one embodiment,an API such as set scheduling policy API 1202 is performed by aprocessor, such as those described herein. In at least one embodiment,an API such as set scheduling policy API 1202 is performed as one ormore steps of a computer-implemented method, as described herein. In atleast one embodiment, an API such as set scheduling policy API 1202 isperformed by one or more processors of a computer system, as describedherein. In at least one embodiment, an API such as set scheduling policyAPI 1202 is stored as instructions on a machine-readable medium, whichcan be performed using one or more processors, as described herein. Inat least one embodiment, an API such as set scheduling policy API 1202,when performed, is to cause a scheduling policy of one or more blocks ofone or more threads to be performed.

In at least one embodiment, set scheduling policy API 1202 is an APIcomprising one or more parameters to cause a scheduling policy of one ormore blocks of one or more threads to be performed. In at least oneembodiment, set scheduling policy API 1202 is an API to indicate ascheduling policy of one or more clusters of one or more groups ofinstructions. In at least one embodiment, set scheduling policy API 1202is an API to set a scheduling policy such as spread scheduling policy1004, described herein at least in connection with FIG. 10 . In at leastone embodiment, set scheduling policy API 1202 is an API to set ascheduling policy such as balance scheduling policy 1104, describedherein at least in connection with FIG. 11 . In at least one embodiment,set scheduling policy API 1202 receives one or more parametersincluding, but not limited to, a scheduling policy attribute 1204, ascheduling policy value 1206, and/or a kernel identifier 1208. In atleast one embodiment, set scheduling policy API 1202 returns a returnvalue 1218.

In at least one embodiment, scheduling policy attribute 1204 of setscheduling policy API 1202 is an attribute that indicates that setscheduling policy API 1202 is setting a scheduling policy value 1206 ofa block cluster. In at least one embodiment, scheduling policy value1206 is a spread scheduling policy, as described herein. In at least oneembodiment, scheduling policy value 1206 is a balance scheduling policy,as described herein. In at least one embodiment, scheduling policy value1206 is a default scheduling policy, as described herein. In at leastone embodiment, kernel identifier 1208 is an identifier of a kernel thatwill be launched using a block cluster with a scheduling policyspecified using set scheduling policy 1202, using systems and methodssuch as those described herein.

In at least one embodiment, not shown in FIG. 12 , set scheduling policyAPI 1202 receives one or more additional parameters and/or of flags thatspecify how scheduling policy attribute 1204, scheduling policy value1206, and/or kernel identifier 1208 will be used to indicate ascheduling policy of a block cluster. In at least one embodiment, whenadditional parameters and/or of flags that specify how scheduling policyattribute 1204, scheduling policy value 1206, and/or kernel identifier1208 will be used to indicate a scheduling policy of a block cluster arenot received, a default set of parameters and/or flags may be used byset scheduling policy API 1202 to indicate a scheduling policy of ablock cluster, using systems and methods such as those described herein.

In at least one embodiment, set scheduling policy API 1202 causes aprocessor such as those described herein to execute one or more commandsto verify block cluster scheduling policy attributes and attributevalues 1210 and set block cluster scheduling policies of a kernel 1212,as identified by kernel identifier 1208. In at least one embodiment, setscheduling policy API 1202 causes a processor such as those describedherein to execute one or more commands to launch a kernel 1214 using ablock cluster as described herein. In at least one embodiment, not shownin FIG. 12 , one or more commands to launch a kernel 1214 are executedat a different time and/or by a different API.

In at least one embodiment, set scheduling policy API 1202 returnssuccess of failure 1216 using return value 1218. In at least oneembodiment, set scheduling policy API 1202 returns success using returnvalue 1218 when set scheduling policy API 1202 sets a block clusterscheduling policy successfully, as described herein. In at least oneembodiment, set scheduling policy API 1202 returns failure using returnvalue 1218 when set scheduling policy API 1202 does not set a blockcluster scheduling policy successfully, as described herein.

In at least one embodiment, set scheduling policy API 1202 returnssuccess or failure 1216 using return value 1218 to a calling processsuch as example process 600 described herein at least in connection withFIG. 6 . In at least one embodiment, set scheduling policy API 1202returns success or failure 1216 using return value 1218 to a callingprocess using integer value, or using a Boolean value, or using anenumerated value, or using a flag, or using a signal, or using asemaphore, or using an event, or using a combination of these and/orother such return value types including, but not limited to, thosedescribed herein.

FIG. 13 illustrates an example application programming interface 1300 toobtain a scheduling policy of a block cluster, in accordance with atleast one embodiment In at least one embodiment, example applicationprogramming interface 1300 to obtain a scheduling policy of a blockcluster is a get scheduling policy API 1302. In at least one embodiment,an API such as get scheduling policy API 1302 is performed by aprocessor, such as those described herein. In at least one embodiment,an API such as get scheduling policy API 1302 is performed as one ormore steps of a computer-implemented method, as described herein. In atleast one embodiment, an API such as get scheduling policy API 1302 isperformed by one or more processors of a computer system, as describedherein. In at least one embodiment, an API such as get scheduling policyAPI 1302 is stored as instructions on a machine-readable medium, whichcan be performed using one or more processors, as described herein. Inat least one embodiment, an API such as get scheduling policy API 1302,when performed, is to indicate a scheduling policy of one or more blocksof one or more threads.

In at least one embodiment, get scheduling policy API 1302 is an APIcomprising one or more parameters to indicate a scheduling policy of oneor more blocks of one or more threads. In at least one embodiment, getscheduling policy API 1302 is an API to obtain a scheduling policy ofone or more clusters of one or more groups of instructions. In at leastone embodiment, get scheduling policy API 1302 is an API to is an API toget a scheduling policy such as spread scheduling policy 1004, describedherein at least in connection with FIG. 10 . In at least one embodiment,get scheduling policy API 1302 is an API to is an API to get ascheduling policy such as balance scheduling policy 1104, describedherein at least in connection with FIG. 11 . In at least one embodiment,get scheduling policy API 1302 receives one or more parametersincluding, but not limited to, a cluster identifier 1304. In at leastone embodiment, get scheduling policy API 1302 returns a return value1312.

In at least one embodiment, cluster identifier 1304 of get schedulingpolicy API 1302 is an identifier used to identify a cluster usingsystems and methods such as those described herein. In at least oneembodiment, for example, cluster identifier 1304 is an indexed value ofa cluster that is based on a total number of clusters of a compute unit.In at least one embodiment, cluster identifier 1304 is a location of acluster within a group of clusters.

In at least one embodiment, not shown in FIG. 13 , get scheduling policyAPI 1302 receives one or more additional parameters and/or of flags thatspecify how cluster identifier 1304 will be used to obtain a schedulingpolicy of a block cluster. In at least one embodiment, when additionalparameters and/or of flags that specify how cluster identifier 1304 willbe used to obtain a scheduling policy of a block cluster are notreceived, one or more default parameters and/or flags may be used by getscheduling policy API 1302 to obtain a scheduling policy of a blockcluster, using systems and methods such as those described herein.

In at least one embodiment, get scheduling policy API 1302 causes aprocessor such as those described herein to execute one or more commandsto determine 1306 whether a scheduling policy of a cluster is set. In atleast one embodiment, if it is determined that a scheduling policy isnot set (“NO” branch), a default return value 1308 may be returned(e.g., a spread scheduling policy). In at least one embodiment, if it isdetermined that a scheduling policy is set (“YES” branch), a schedulingpolicy of cluster is returned. In at least one embodiment, getscheduling policy API 1302 returns a scheduling policy 1310 using returnvalue 1312.

In at least one embodiment, get scheduling policy API 1302 returns ascheduling policy 1310 using return value 1312 to a calling process suchas example process 600 described herein at least in connection with FIG.6 . In at least one embodiment, get scheduling policy API 1302 returns ascheduling policy 1310 using return value 1312 to a calling processusing integer value, or using a Boolean value, or using an enumeratedvalue, or using a flag, or using a signal, or using a semaphore, orusing an event, or using a combination of these and/or other such returnvalue types including, but not limited to, those described herein.

FIG. 14 illustrates an example computer system 1400 where a maximumnumber of clusters supported by hardware is obtained, in accordance withat least one embodiment. In at least one embodiment, a processor 1402(which is a processor such as processor 102, described herein at leastin connection with FIG. 1 ), executes or otherwise performs one or morecommands to request a number of clusters supported 1404 that can be usedto execute a kernel, as described herein. In at least one embodiment,processor 1402 executes or otherwise performs one or more commands torequest a number of clusters supported 1404 that can be used to executea kernel based, at least in part, on a configuration (not shown in FIG.14 ). In at least one embodiment, processor 1402 executes or otherwiseperforms one or more commands to request a number of clusters supported1404 that can be used to execute a kernel based using number of blockssupported API 1502, described herein at least in connection with FIG. 15.

In at least one embodiment, a graphics processor 1406 (which is agraphics processor such as graphics processor 108, described herein atleast in connection with FIG. 1 ), determines a maximum number ofclusters 1408 that can be used to execute a kernel. In at least oneembodiment, graphics processor 1406 determines a maximum number ofclusters 1408 that can be used to execute a kernel based at least onkernel parameters, a kernel configuration, hardware capabilities ofgraphics processor 1406, available resources, and/or other such factors.In at least one embodiment, graphics processor 1406 returns a determinedmaximum number of clusters 1410 to processor 1402 using methods such asthose described herein.

In at least one embodiment, not illustrated in FIG. 14 , a processorsuch as processor 1402 determines information such as, for example, amaximum number of clusters supported by hardware, without executing orotherwise performing one or more commands to request a number ofclusters supported 1404 that can be used to execute a kernel. In such anembodiment, processor 1402 may store information such as maximum numberof clusters 1408 in memory associated with processor 1402.

FIG. 15 illustrates an example application programming interface 1500 toobtain a maximum number of clusters supported by hardware, in accordancewith at least one embodiment. In at least one embodiment, exampleapplication programming interface 1500 to obtain a maximum number ofclusters supported by hardware is a number of blocks supported API 1502.In at least one embodiment, an API such as number of blocks supportedAPI 1502 is performed by a processor, such as those described herein. Inat least one embodiment, an API such as number of blocks supported API1502 is performed as one or more steps of a computer-implemented method,as described herein. In at least one embodiment, an API such as numberof blocks supported API 1502 is performed by one or more processors of acomputer system, as described herein. In at least one embodiment, an APIsuch as number of blocks supported API 1502 is stored as instructions ona machine-readable medium, which can be performed using one or moreprocessors, as described herein. In at least one embodiment, an API suchas number of blocks supported API 1502, when performed, is to indicate amaximum number of blocks of threads capable of being scheduled inparallel.

In at least one embodiment, number of blocks supported API 1502 is anAPI to indicate a maximum number of blocks of threads capable of beingscheduled in parallel. In at least one embodiment, number of blockssupported API 1502 is an API to obtain a limit of a number of allowableclusters of one or more groups of instructions. In at least oneembodiment, number of blocks supported API 1502 is an API to request amaximum number of clusters supported 1404, as described herein at leastin connection with FIG. 14 . In at least one embodiment, number ofblocks supported API 1502 receives one or more parameters including, butnot limited to, a stored number of clusters 1504, a kernel 1506, and/ora launch configuration 1508. In at least one embodiment, number ofblocks supported API 1502 returns a return value 1516.

In at least one embodiment, stored number of clusters 1504 is a locationthat is used by get of number of blocks supported API 1502 to return anumber of clusters supported by hardware. In at least one embodiment,kernel 1506 is a kernel that will be executed by graphics hardware usingsystems and methods such as those described herein. In at least oneembodiment, launch configuration 1508 includes one or more parameterssuch as those described herein that may be used to launch kernel 1506using block clusters, as described herein.

In at least one embodiment, not shown in FIG. 15 , number of blockssupported API 1502 receives one or more additional parameters and/or offlags that specify how kernel 1506 and/or launch configuration 1508 willbe used to obtain a maximum number of clusters supported by hardware. Inat least one embodiment, when additional parameters and/or of flags thatspecify how kernel 1506 and/or launch configuration 1508 will be used toobtain a maximum number of clusters supported by hardware are notreceived, one or more default parameters and/or flags may be used bynumber of blocks supported API 1502 to obtain a maximum number ofclusters supported by hardware, using systems and methods such as thosedescribed herein.

In at least one embodiment, number of blocks supported API 1502 causes aprocessor such as those described herein to execute one or more commandsto determine number of clusters 1510 using systems and methods such asthose described herein at least in connection with FIG. 14 and stores adetermined value 1512 in stored number of clusters 1504. In at least oneembodiment, number of blocks supported API 1502 returns success orfailure 1514 using return value 1516. In at least one embodiment, numberof blocks supported API 1502 returns success using return value 1516when a number of clusters is determined. In at least one embodiment,number of blocks supported API 1502 returns failure using return value1516 when a number of clusters is not determined or when a sufficientnumber of clusters is not available.

In at least one embodiment, number of blocks supported API 1502 returnssuccess or failure 1514 using return value 1516 to a calling processsuch as example process 600 described herein at least in connection withFIG. 6 . In at least one embodiment, number of blocks supported API 1502returns success or failure 1514 using return value 1516 to a callingprocess using integer value, or using a Boolean value, or using anenumerated value, or using a flag, or using a signal, or using asemaphore, or using an event, or using a combination of these and/orother such return value types including, but not limited to, thosedescribed herein.

FIG. 16 illustrates an example diagram 1600 where block clusterattributes are indicated and obtained, in accordance with at least oneembodiment. In at least one embodiment, a cluster size must be set atlaunch attribute 1602 is used to determine whether a cluster size mustbe sent at launch of a cluster. In at least one embodiment, cluster sizemust be set at launch attribute 1602 is used by indicate clusterparameters API 1702, described herein at least in connection with FIG.17 , to determine whether a cluster size must be sent at launch of acluster. In at least one embodiment, cluster size must be set at launchattribute 1602 that is false indicates that a block cluster such asthose described herein can be launched without a set cluster size and,in such an embodiment, a block cluster can be launched without a setcluster size. In at least one embodiment, cluster size must be set atlaunch attribute 1602 that is true indicates that a block cluster suchas those described herein cannot be launched without a set cluster sizeand, in such an embodiment, a block cluster cannot be launched without aset cluster size. In at least one embodiment, a graphics processor 1606(which is a graphics processor such as graphics processor 108, describedherein at least in connection with FIG. 1 ) determines an attributevalue 1608 of a cluster size must be set at launch attribute 1602 andreturns an attribute value 1604 to a calling thread or process (e.g., acalling thread or process that performs indicate cluster parameters API1702, described herein at least in connection with FIG. 17 ). In atleast one embodiment, as illustrated in FIG. 16 , cluster size must beset at launch attribute 1602 is read-only (e.g., cannot be set by acalling process). In at least one embodiment, not illustrated in FIG. 16, cluster size must be set at launch attribute 1602 is writable (e.g.,can be set by a calling process).

In at least one embodiment, a non-portable cluster size allowedattribute 1610 is used to determine whether a non-portable (e.g., notforward compatible) cluster size can be used to launch of a cluster. Inat least one embodiment, non-portable cluster size allowed attribute1610 is used by indicate cluster parameters API 1702, described hereinat least in connection with FIG. 17 , to determine whether anon-portable (e.g., not forward compatible) cluster size can be used tolaunch of a cluster. In at least one embodiment, a non-portable clustersize is a cluster size that may not be supported in other hardwareconfigurations of graphics processor 1606 but is supported by a currenthardware configuration of graphics processor 1606. In at least oneembodiment, non-portable cluster size allowed attribute 1610 that istrue indicates that a block cluster such as those described herein canbe launched with a non-portable cluster size and, in such an embodiment,a block cluster can be launched with a non-portable cluster size. In atleast one embodiment, non-portable cluster size allowed attribute 1610that is false indicates that a block cluster such as those describedherein cannot be launched with a non-portable cluster size and, in suchan embodiment, a block cluster cannot be launched with a non-portablecluster size. In at least one embodiment, a graphics processor 1606determines an attribute value 1614 of a non-portable cluster sizeallowed attribute 1610 and returns an attribute value 1612 to a callingthread or process (e.g., a calling thread or process that performsindicate cluster parameters API 1702, described herein at least inconnection with FIG. 17 ). In at least one embodiment, as illustrated inFIG. 16 , non-portable cluster size allowed attribute 1610 is read-write(e.g., can be set by a calling process). In at least one embodiment, notillustrated in FIG. 16 , non-portable cluster size allowed attribute1610 is read-only (e.g., cannot be set by a calling process).

In at least one embodiment, one or more other attributes 1616 of a blockcluster can be indicated and/or obtained including, but not limited,those described herein such as, for example, cluster size, clusterdimension, cluster scheduling policies, etc. In at least one embodiment,one or more other attributes 1616 of a block cluster are used byindicate cluster parameters API 1702, described herein at least inconnection with FIG. 17 , to determine one or more other attributes of acluster. In at least one embodiment, graphics processor 1606 determinedattribute values 1620 of one or more other attributes 1616 and returnsone or more attribute values 1618 to a calling process. In at least oneembodiment, at least one of one or more other attributes 1616 isread-write (e.g., can be set by a calling process). In at least oneembodiment, at least one of one or more other attributes 1616 isread-only (e.g., cannot be set by a calling process).

FIG. 17 illustrates an example application programming interface 1700 toindicate and obtain attributes of block clusters, in accordance with atleast one embodiment. In at least one embodiment, example applicationprogramming interface 1700 to indicate and obtain attributes of blockclusters is an indicate cluster parameters API 1702. In at least oneembodiment, an API such as indicate cluster parameters API 1702 isperformed by a processor, such as those described herein. In at leastone embodiment, an API such as indicate cluster parameters API 1702 isperformed as one or more steps of a computer-implemented method, asdescribed herein. In at least one embodiment, an API such as indicatecluster parameters API 1702 is performed by one or more processors of acomputer system, as described herein. In at least one embodiment, an APIsuch as indicate cluster parameters API 1702 is stored as instructionson a machine-readable medium, which can be performed using one or moreprocessors, as described herein. In at least one embodiment, an API suchas indicate cluster parameters API 1702, when performed, is to indicateone or more attributes of one or more groups of blocks of one or morethreads.

In at least one embodiment, indicate cluster parameters API 1702 is anAPI comprising one or more parameters to indicate one or more attributesof one or more groups of blocks of one or more threads. In at least oneembodiment, indicate cluster parameters API 1702 is an API to obtain oneor more attributes of one or more clusters of one or more groups ofinstructions. In at least one embodiment, indicate cluster parametersAPI 1702 is an API to get or set cluster attributes as described hereinat least in connection with FIG. 16 . In at least one embodiment,indicate cluster parameters API 1702 receives one or more parametersincluding, but not limited to, an attribute 1704, an attribute value1706, and an indicator 1708 as to whether to set or get an attribute. Inat least one embodiment, indicate cluster parameters API 1702 returnsreturn value 1728.

In at least one embodiment, attribute 1704 of indicate clusterparameters API 1702 is an attribute such as those described herein thatindicates one or more parameters of one or more block clusters. In atleast one embodiment, attribute value 1706 of indicate clusterparameters API 1702 is a value of attribute 1704. In at least oneembodiment, indicator 1708 of indicate cluster parameters API 1702 isused to determine whether a value stored in attribute value 1706 is usedto set an attribute 1704 or is used to store a value of an attribute1704.

In at least one embodiment, not shown in FIG. 17 , indicate clusterparameters API 1702 receives one or more additional parameters and/or offlags that specify how attribute 1704, attribute value 1706, and/orindicator 1708 will be used to indicate and/or obtain attributes ofblock clusters. In at least one embodiment, when additional parametersand/or of flags that specify how attribute 1704, attribute value 1706,and/or indicator 1708 will be used to indicate and/or obtain attributesof block clusters are not received, one or more default parametersand/or flags may be used by indicate cluster parameters API 1702 toindicate and/or obtain attributes of block clusters, using systems andmethods such as those described herein.

In at least one embodiment, indicate cluster parameters API 1702 causesa processor such as those described herein to execute one or morecommands to determine 1712 whether indicator 1708 is to get or to set avalue of an attribute. In at least one embodiment, if it is determinedthat indicator 1708 is to get an attribute (“GET” branch), indicatecluster parameters API 1702 causes a processor such as those describedherein to execute one or more commands to get an attribute 1714, storean attribute 1716 (e.g., using storage in attribute value 1706), andreturn success 1718 using return value 1728.

In at least one embodiment, if it is determined that indicator 1708 isto set an attribute (“SET” branch), indicate cluster parameters API 1702causes a processor such as those described herein to execute one or morecommands to determine 1720 whether an attribute is settable. In at leastone embodiment, if it is determined that an attribute is not settable(“NO” branch), indicate cluster parameters API 1702 causes a processorsuch as those described herein to execute one or more commands to returnfailure 1722 using return value 1728. In at least one embodiment, if itis determined that an attribute is settable (“YES” branch), indicatecluster parameters API 1702 causes a processor such as those describedherein to execute one or more commands to set an attribute 1724 usingattribute value 1706 and to return success 1726 using return value 1728.

In at least one embodiment, indicate cluster parameters API 1702 returnssuccess 1718, returns failure 1722, or returns success 1726 using returnvalue 1728 to a calling process such as example process 600 describedherein at least in connection with FIG. 6 . In at least one embodiment,indicate cluster parameters API 1702 returns success 1718, returnsfailure 1722, or returns success 1726 using return value 1728 to acalling process using integer value, or using a Boolean value, or usingan enumerated value, or using a flag, or using a signal, or using asemaphore, or using an event, or using a combination of these and/orother such return value types including, but not limited to, thosedescribed herein.

FIG. 18 illustrates an example computer system 1800 where a maximumcluster size that can be simultaneously performed is obtained, inaccordance with at least one embodiment. In at least one embodiment, aprocessor 1802 (which is a processor such as processor 102, describedherein at least in connection with FIG. 1 ), executes or otherwiseperforms one or more commands to request a maximum cluster size that canbe supported by graphics hardware 1804, as described herein. In at leastone embodiment, processor 1802 executes or otherwise performs one ormore commands to request a maximum cluster size that can be supported bygraphics hardware 1804 to execute a kernel based, at least in part, on aconfiguration (not shown in FIG. 18 ). In at least one embodiment,processor 1802 executes or otherwise performs one or more commands torequest a maximum cluster size that can be concurrently executed bygraphics hardware.

In at least one embodiment, a graphics processor 1806 (which is agraphics processor such as graphics processor 108, described herein atleast in connection with FIG. 1 ), determines a maximum cluster size1808 that can be used to execute a kernel. In at least one embodiment,graphics processor 1806 determines a maximum cluster size 1808 that canbe used to execute a kernel based at least on kernel parameters, akernel configuration, hardware capabilities of graphics processor 1806,available resources, and/or other such factors. In at least oneembodiment, graphics processor 1806 returns a determined maximum clustersize 1810 to processor 1802 using methods such as those describedherein.

In at least one embodiment, not illustrated in FIG. 18 , a processorsuch as processor 1802 determines information such as, for example, amaximum cluster size that can be simultaneously performed, withoutexecuting or otherwise performing one or more commands to request amaximum cluster size that can be supported by graphics hardware 1804 toexecute a kernel. In such an embodiment, processor 1802 may storeinformation such as maximum cluster size 1808 in memory associated withprocessor 1802.

FIG. 19 illustrates an example application programming interface 1900 toobtain a maximum cluster size that can be simultaneously performed byhardware, in accordance with at least one embodiment. In at least oneembodiment, example application programming interface 1900 to obtain amaximum cluster size that can be simultaneously performed by hardware isa maximum cluster size supported API 1902. In at least one embodiment,an API such as maximum cluster size supported API 1902 is performed by aprocessor, such as those described herein. In at least one embodiment,an API such as maximum cluster size supported API 1902 is performed asone or more steps of a computer-implemented method, as described herein.In at least one embodiment, an API such as maximum cluster sizesupported API 1902 is performed by one or more processors of a computersystem, as described herein. In at least one embodiment, an API such asmaximum cluster size supported API 1902 is stored as instructions on amachine-readable medium, which can be performed using one or moreprocessors, as described herein. In at least one embodiment, an API suchas maximum cluster size supported API 1902, when performed, is toindicate a maximum number of blocks of threads to be scheduled inparallel.

In at least one embodiment, maximum cluster size supported API 1902 isan API to indicate a maximum number of blocks of threads to be scheduledin parallel. In at least one embodiment, maximum cluster size supportedAPI 1902 is an API to obtain a limit of a number of concurrentlyperformable clusters of one or more groups of instructions. In at leastone embodiment, maximum cluster size supported API 1902 is an API todetermine a request a maximum cluster size that can be supported bygraphics hardware 1804, as described herein at least in connection withFIG. 18 . In at least one embodiment, maximum cluster size supported API1902 receives one or more parameters including, but not limited to, astored maximum cluster size 1904, a kernel 1906, and/or a launchconfiguration 1908. In at least one embodiment, maximum cluster sizesupported API 1902 returns a return value 1916.

In at least one embodiment, stored maximum cluster size 1904 is alocation that is used by maximum cluster size supported API 1902 toreturn a maximum cluster size that can be simultaneously performed byhardware. In at least one embodiment, kernel 1906 is a kernel that willbe executed by graphics hardware using systems and methods such as thosedescribed herein. In at least one embodiment, launch configuration 1908includes one or more parameters such as those described herein that maybe used to launch kernel 1906 using block clusters, as described herein.

In at least one embodiment, not shown in FIG. 19 , maximum cluster sizesupported API 1902 receives one or more additional parameters and/or offlags that specify kernel 1906 and/or launch configuration 1908 will beused to obtain a maximum cluster size that can be simultaneouslyperformed by hardware. In at least one embodiment, when additionalparameters and/or of flags that specify how kernel 1906 and/or launchconfiguration 1908 will be used to obtain a maximum cluster size thatcan be simultaneously performed by hardware are not received, one ormore default parameters and/or flags may be used by maximum cluster sizesupported API 1902 to obtain a maximum cluster size that can besimultaneously performed by hardware, using systems and methods such asthose described herein.

In at least one embodiment, maximum cluster size supported API 1902causes a processor such as those described herein to execute one or morecommands to determine maximum cluster size 1910 using systems andmethods such as those described herein at least in connection with FIG.18 and stores a determined value 1912 in stored maximum cluster size1904. In at least one embodiment, maximum cluster size supported API1902 returns success or failure 1914 using return value 1916. In atleast one embodiment, maximum cluster size supported API 1902 returnssuccess using return value 1916 when a maximum cluster size isdetermined. In at least one embodiment, maximum cluster size supportedAPI 1902 returns failure using return value 1916 when a maximum clustersize is not determined.

In at least one embodiment, maximum cluster size supported API 1902returns success or failure 1914 using return value 1916 to a callingprocess such as example process 600 described herein at least inconnection with FIG. 6 . In at least one embodiment, maximum clustersize supported API 1902 returns success or failure 1914 using returnvalue 1916 to a calling process using integer value, or using a Booleanvalue, or using an enumerated value, or using a flag, or using a signal,or using a semaphore, or using an event, or using a combination of theseand/or other such return value types including, but not limited to,those described herein.

FIG. 20 illustrates an example computer system 2000 where a softwarekernel is executed using block clusters, in accordance with at least oneembodiment. In at least one embodiment, a processor 2002 (which is aprocessor such as processor 102, described herein at least in connectionwith FIG. 1 ) executes or otherwise performs one or more commends toreceive cluster parameters 2004, generate a kernel 2006, and launch akernel 2008 using block clusters, based at least in part on clusterparameters 2004, using systems and methods such as those describedherein.

In at least one embodiment, when cluster parameters 2004 indicate aspread scheduling policy as described herein, processor 2002 launcheskernel 2008 using a first block cluster 2014 on compute unit 2014 usinggraphics processor 2010 (which is a graphics processor such as graphicsprocessor 108, described herein at least in connection with FIG. 1 ) andusing a second block cluster 2018 on compute unit 2016 using graphicsprocessor 2010. In at least one embodiment, not illustrated in FIG. 20 ,when cluster parameters 2004 indicate a balance scheduling policy asdescribed herein, processor 2002 may launch kernel 2008 using a firstblock cluster 2014 on compute unit 2014 and may also launch second blockcluster 2018 on compute unit 2014 or may launch kernel 2008 using afirst block cluster 2014 on compute unit 2016 and may also launch secondblock cluster 2018 on compute unit 2016, or may launch kernel 2008 usingsome other distribution of block clusters, based at least in part oncluster parameters 2004.

FIG. 21 illustrates an example application programming interface 2100 toexecute a software kernel using block clusters, in accordance with atleast one embodiment. In at least one embodiment, example applicationprogramming interface 2100 to execute a software kernel using blockclusters is a launch kernel with block clusters API 2102. In at leastone embodiment, an API such as launch kernel with block clusters API2102 is performed by a processor, such as those described herein. In atleast one embodiment, an API such as launch kernel with block clustersAPI 2102 is performed as one or more steps of a computer-implementedmethod, as described herein. In at least one embodiment, an API such aslaunch kernel with block clusters API 2102 is performed by one or moreprocessors of a computer system, as described herein. In at least oneembodiment, an API such as launch kernel with block clusters API 2102 isstored as instructions on a machine-readable medium, which can beperformed using one or more processors, as described herein. In at leastone embodiment, an API such as launch kernel with block clusters API2102, when performed, is to cause a kernel to be generated to cause twoor more blocks of two or more threads to be scheduled in parallel.

In at least one embodiment, launch kernel with block clusters API 2102is an API to cause a kernel to be generated to cause two or more blocksof two or more threads to be scheduled in parallel. In at least oneembodiment, launch kernel with block clusters API 2102 is an API tocause a software kernel to be performed using one or more clusters ofone or more groups of instructions. In at least one embodiment, launchkernel with block clusters API 2102 is an API to launch a kernel usingblock clusters as described herein at least in connection with FIG. 20 .In at least one embodiment, launch kernel with block clusters API 2102receives one or more parameters including, but not limited to, a kernel2104 and one or more cluster parameters 2106 such as those describedherein (e.g., cluster dimensions, cluster scheduling policy, etc.). Inat least one embodiment, launch kernel with block clusters API 2102returns a return value 2114.

In at least one embodiment, kernel 2104 of launch kernel with blockclusters API 2102 is an identifier of a kernel to launch using blockclusters, using systems and methods such as those described herein andcluster parameters 2116 are parameters such as those described hereinthat are used to specify how a kernel 2104 is to be launched using blockclusters. In at least one embodiment, not shown in FIG. 21 , launchkernel with block clusters API 2102 receives one or more additionalparameters and/or of flags that specify how kernel 2104 and/or clusterparameters 2106 will be used to execute a software kernel using blockclusters. In at least one embodiment, when additional parameters and/orof flags that specify how kernel 2104 and/or cluster parameters 2106will be used to execute a software kernel using block clusters are notreceived, one or more default parameters and/or flags may be used bylaunch kernel with block clusters API 2102 to execute a software kernelusing block clusters, using systems and methods such as those describedherein.

In at least one embodiment, launch kernel with block clusters API 2102causes a processor such as those described herein to execute one or morecommands to validate one or more cluster parameters 2108 as describedherein, to launch a kernel using block clusters 2110, and to returnsuccess or failure 2112 using return value 2114. In at least oneembodiment, launch kernel with block clusters API 2102 returns successusing return value 2114 when launch kernel with block clusters API 2102does successfully launch a kernel using block clusters 2110. In at leastone embodiment, launch kernel with block clusters API 2102 returnsfailure using return value 2114 when launch kernel with block clustersAPI 2102 does not successfully launch a kernel using block clusters2110.

In at least one embodiment, launch kernel with block clusters API 2102returns success or failure 2112 using return value 2114 to a callingprocess such as example process 600 described herein at least inconnection with FIG. 6 . In at least one embodiment, launch kernel withblock clusters API 2102 returns success or failure 2112 using returnvalue 2114 to a calling process using integer value, or using a Booleanvalue, or using an enumerated value, or using a flag, or using a signal,or using a semaphore, or using an event, or using a combination of theseand/or other such return value types including, but not limited to,those described herein.

FIG. 22 illustrates an example diagram 2200 where a hierarchy ofthreads, thread blocks, block clusters, compute units, and graphicsprocessors is shown, in accordance with at least one embodiment. In atleast one embodiment, a graphics processor 2202 (which is a graphicsprocessor such as graphics processor 102, described herein at least inconnection with FIG. 1 ) includes one or more compute units. In at leastone embodiment, graphics processor 2202 includes a first compute unit2204 (which is a compute unit such as compute unit 110, described hereinat least in connection with FIG. 1 ). In at least one embodiment,compute unit 2204 includes one or more block clusters. In at least oneembodiment, compute unit 2204 includes a first block cluster 2208 (whichis a block cluster such as block cluster 112, block cluster 118, and/orblock cluster 120, all described herein at least in connection with FIG.1 ). In at least one embodiment, block cluster 2208 includes one or morethread blocks. In at least one embodiment, block cluster 2208 includes afirst thread block 2212 (which is a thread block such as thread block202, described herein at least in connection with FIG. 2 ). In at leastone embodiment, thread block 2212 includes one or more threads (e.g.,thread 2216, thread 2218, etc.), which are threads such as thosedescribed herein.

In at least one embodiment, graphics processor 2202 includes one or moreadditional compute units (e.g., compute unit 2206). In at least oneembodiment, a compute unit such as compute unit 2206 can include one ormore block clusters, not illustrated in FIG. 22 . In at least oneembodiment, compute unit 2204 includes one or more additional blockclusters (e.g., block cluster 2210). In at least one embodiment, blockclusters such as block cluster 2210 can include one or more threadblocks, not illustrated in FIG. 22 . In at least one embodiment, blockcluster 2208 includes one or more additional thread blocks (e.g., threadblock 2214). In at least one embodiment, a thread block such as threadblock 2214 can include one or more threads, not illustrated in FIG. 22 .

In at least one embodiment, a block cluster such as block cluster 2208executes on multiple compute units, as described herein. In at least oneembodiment, a block cluster such as block cluster 2208 executes on aportion of compute units of a graphics processor such as graphicsprocessor 2202. In at least one embodiment, a block cluster such asblock cluster 2208 executes on all compute units of a graphics processorsuch as graphics processor 2202. In at least one embodiment, a blockcluster such as block cluster 2208 executes on a plurality of graphicsprocessors such as graphics processor 2202 so that, for example, a firstset of thread blocks of a block cluster execute on a first compute unitof a first graphics processor, a second set of thread blocks of a blockcluster execute on a second compute unit of a first graphics processor,a third set of thread blocks of a block cluster execute on a firstcompute unit of a second graphics processor, a fourth set of threadblocks of a block cluster execute on a second compute unit of a secondgraphics processor, etc. In at least one embodiment, a plurality ofgraphics processors are graphics processors of a compute cluster ofgraphics processors that are connected using one or more technologiessuch as those described herein. In at least one embodiment, a graphicsprocessor such as graphics processor 2202 is a virtual graphicsprocessor that spans (or includes) a plurality of physical graphicsprocessors such as those described herein.

FIG. 23 illustrates an example diagram 2300 where thread attributes of acalling thread are obtained, in accordance with at least one embodiment.In at least one embodiment, a calling thread 2306 executes or otherwiseperforms one or more commands to get thread block and/or block clusterattributes 2320 associated with calling thread 2306. In at least oneembodiment, calling thread 2306 executes or otherwise performs one ormore commands to get thread block and/or block cluster attributes 2320associated with calling thread 2306 using get attributes API 2602,described herein at least in connection with FIG. 26 . In at least oneembodiment, some other process or processor executes or otherwiseperforms one or more commands to get thread block and/or block clusterattributes 2320 associated with calling thread 2306 using get attributesAPI 2602 such as, for example, a process operating on a CPU or a GPU,such as those described herein. In at least one embodiment, callingthread 2306 is a thread of thread block 2304 (e.g., a thread block suchas those described herein), which has n₁ threads (e.g., calling thread2306 and n₁−1 other threads such as thread 2308 to thread 2310). In atleast one embodiment, thread block 2304 is a thread block of blockcluster 2302 (e.g., a block cluster such as those described herein),which has thread block 2312 with n₂ threads, thread block 2314 with n₃threads, etc.

In at least one embodiment, calling thread 2306 executes or otherwiseperforms one or more commands to get thread block and/or block clusterattributes 2320 including, for example, a number of threads in a cluster2316, which returns a total number of threads in block cluster 2302(e.g., n=n₁+n₂+n₃+ . . . ). In at least one embodiment, an attributesuch as number of threads in a cluster 2316 is referred to asthread-level information. In at least one embodiment, an attribute suchas number of threads in a cluster 2316 is referred to as cluster-levelinformation. In at least one embodiment, calling thread 2306 executes orotherwise performs one or more commands to get thread block and/or blockcluster attributes 2320 including, for example, an identifier 2318 ofcalling thread 2306, which returns an index (or rank) from [1, n] wheren is a total number of threads in block cluster 2302. In at least oneembodiment, an attribute such as identifier 2318 of calling thread 2306is referred to as thread-level information.

FIG. 24 illustrates an example diagram 2400 where block clusterattributes of a calling thread are obtained, in accordance with at leastone embodiment. In at least one embodiment, a calling thread 2406executes or otherwise performs one or more commands to get thread blockand/or block cluster attributes 2416 associated with calling thread2406. In at least one embodiment, calling thread 2406 executes orotherwise performs one or more commands to get thread block and/or blockcluster attributes 2416 associated with calling thread 2406 using getattributes API 2602, described herein at least in connection with FIG.26 . In at least one embodiment, some other process or processorexecutes or otherwise performs one or more commands to get thread blockand/or block cluster attributes 2416 associated with calling thread 2406using get attributes API 2602 such as, for example, a process operatingon a CPU or a GPU, such as those described herein. In at least oneembodiment, calling thread 2406 is a thread of thread block 2404, whichmay include one or more other threads (e.g., thread 2408). In at leastone embodiment, thread block 2404 is a thread block of block cluster2402, which includes B_(x)×B_(y)×B, thread blocks (e.g., thread block2410, thread block 2412, thread block 2414, etc.).

In at least one embodiment, calling thread 2406 executes or otherwiseperforms one or more commands to get thread block and/or block clusterattributes 2416 including, for example, dimensions of a cluster 2418,which returns a three-dimensional size of block cluster 2402 (e.g.,(B_(x), B_(y), B_(z))). In at least one embodiment, an attribute such asdimensions of a cluster 2418 is referred to as cluster-levelinformation. In at least one embodiment, calling thread 2406 executes orotherwise performs one or more commands to get thread block and/or blockcluster attributes 2416 including, for example, a block index 2420 ofthread block 2404 of calling thread 2406, which returns athree-dimensional index of thread block 2404 (e.g., an index from([1,B_(x)], [1,B_(y)], [1,B_(z)])). In at least one embodiment, anattribute such as block index 2420 of thread block 2404 of callingthread 2406 is referred to as block-level information. In at least oneembodiment, calling thread 2406 executes or otherwise performs one ormore commands to get thread block and/or block cluster attributes 2416including, for example, a number of blocks in a cluster 2422, whichreturns a total number of blocks in block cluster 2402 (e.g.,B_(x)×B_(y)×B_(z)) (e.g., cluster-level information) In at least oneembodiment, calling thread 2406 executes or otherwise performs one ormore commands to get thread block and/or block cluster attributes 2416including, for example, a block identifier 2424 of a thread block 2404of calling thread 2406, which returns an index of thread block 2404(e.g., from [1, B_(x)×B_(y)×B_(z)]) (e.g., block-level information).

FIG. 25 illustrates an example diagram 2500 where block cluster groupattributes of a calling thread are obtained, in accordance with at leastone embodiment. In at least one embodiment, a calling thread 2508executes or otherwise performs one or more commands to get thread block,block cluster, and/or compute unit attributes 2522 associated withcalling thread 2508. In at least one embodiment, calling thread 2508executes or otherwise performs one or more commands to get thread block,block cluster, and/or compute unit attributes 2522 associated withcalling thread 2508 using get attributes API 2602, described herein atleast in connection with FIG. 26 . In at least one embodiment, someother process or processor executes or otherwise performs one or morecommands to get thread block, block cluster, and/or compute unitattributes 2522 associated with calling thread 2508 using get attributesAPI 2602 such as, for example, a process operating on a CPU or a GPU,such as those described herein. In at least one embodiment, callingthread 2508 is a thread of thread block 2506. In at least oneembodiment, thread block 2506 is a thread block of block cluster 2504.In at least one embodiment, block cluster 2504 includes one or moreadditional thread blocks (e.g., thread block 2510, thread block 2512,thread block 2514, etc.). In at least one embodiment, block cluster 2504is a block cluster of compute unit 2502. In at least one embodiment,compute unit 2502 includes C_(x)×C_(y)×C_(z) block clusters (e.g., blockcluster 2516, block cluster 2518, block cluster 2520, etc.).

In at least one embodiment, calling thread 2508 executes or otherwiseperforms one or more commands to get thread block, block cluster, and/orcompute unit attributes 2522 including, for example, cluster dimensionsof a grid 2524, which returns a three-dimensional size of block clustersin compute unit 2502 (e.g., (C_(x), C_(y), C_(z))). In at least oneembodiment, calling thread 2508 executes or otherwise performs one ormore commands to get thread block, block cluster, and/or compute unitattributes 2522 including, for example, a cluster index 2526 of blockcluster 2504 of thread block 2506 of calling thread 2508, which returnsa three-dimensional index of block cluster 2504 (e.g., an index from([1,C_(x)], [1,C_(y)], [1,C_(z)])). In at least one embodiment, callingthread 2508 executes or otherwise performs one or more commands to getthread block, block cluster, and/or compute unit attributes 2522including, for example, a number of block clusters of grid 2528, whichreturns a total number of block clusters of compute unit 2502 (e.g.,C_(x)×C_(y)×C_(z)). In at least one embodiment, calling thread 2508executes or otherwise performs one or more commands to get thread block,block cluster, and/or compute unit attributes 2522 including, forexample, a block cluster identifier 2530 of block cluster 2504 of threadblock 2506 of calling thread 2508, which returns an index of blockcluster 2504 (e.g., from [1, C_(x)×C_(y)×C_(z)]).

FIG. 26 illustrates an example application programming interface 2600 toobtain thread, thread block, block cluster, and block cluster groupattributes of a calling thread, in accordance with at least oneembodiment. In at least one embodiment, example application programminginterface 2600 to obtain thread, thread block, block cluster, and blockcluster group attributes of a calling thread is a get attributes API2602. In at least one embodiment, an API such as get attributes API 2602is performed by a processor, such as those described herein. In at leastone embodiment, an API such as get attributes API 2602 is performed asone or more steps of a computer-implemented method, as described herein.In at least one embodiment, an API such as get attributes API 2602 isperformed by one or more processors of a computer system, as describedherein. In at least one embodiment, an API such as get attributes API2602 is stored as instructions on a machine-readable medium, which canbe performed using one or more processors, as described herein. In atleast one embodiment, an API such as get attributes API 2602, whenperformed, is to indicate one or more limitations of one or moreattributes of one or more groups of blocks of one or more threads.

In at least one embodiment, get attributes API 2602 is an API comprisingone or more parameters to indicate one or more limitations of one ormore attributes of one or more groups of blocks of one or more threads.In at least one embodiment, get attributes API 2602 is an API to obtainone or more parameters of one or more clusters of one or more groups ofinstructions of a set of one or more clusters of one or more groups ofinstructions. In at least one embodiment, get attributes API 2602 is anAPI to obtain thread block, block cluster, and/or compute unitattributes of a calling thread as described herein at least inconnection with FIGS. 23-25 . In at least one embodiment, get attributesAPI 2602 receives one or more parameters including, but not limited to,a calling thread ID 2604, an attribute 2606, and/or an attribute type2608. In at least one embodiment, get attributes API 2602 returns areturn value 2616.

In at least one embodiment, calling thread ID 2604 of get attributes API2602 is an identifier of a calling thread that calls get attributes API2602 and attribute 2606 of get attributes API 2602 is an attribute ofcalling thread identified by calling thread ID 2604 such as thosedescribed herein at least in connection with FIGS. 23-25 . In at leastone embodiment, attribute type 2608 of get attributes API 2602 is areturn type of attribute 2606 (e.g., a value, or a three-dimensionalvalue, etc.).

In at least one embodiment, not shown in FIG. 26 , get attributes API2602 receives one or more additional parameters and/or of flags thatspecify how attribute 2606 and/or attribute type 2608 will be used toobtain thread, thread block, block cluster, and block cluster groupattributes of a calling thread identified by calling thread ID 2604(e.g., attributes of a thread hierarchy of which a calling threadidentified by calling thread ID 2604 is a member). In at least oneembodiment, when additional parameters and/or of flags that specify howattribute 2606 and/or attribute type 2608 will be used to obtain thread,thread block, block cluster, and block cluster group attributes of acalling thread identified by calling thread ID 2604 (e.g., attributes ofa thread hierarchy of which a calling thread identified by callingthread ID 2604 is a member) are not received, one or more defaultparameters and/or flags may be used by get attributes API 2602 to obtainthread, thread block, block cluster, and block cluster group attributesof a calling thread, using systems and methods such as those describedherein.

In at least one embodiment, get attributes API 2602 causes a processorsuch as those described herein to execute one or more commands toidentify 2610 a thread, thread block, block cluster, and/or grid of acalling thread identified by calling thread ID 2604 and to determine2612 a value of a requested attribute 2606, as described herein. In atleast one embodiment, get attributes API 2602 returns a determinedattribute 2614 using return value 2616.

In at least one embodiment, get attributes API 2602 returns a determinedattribute 2614 using return value 2616 to a calling process such asexample process 600 described herein at least in connection with FIG. 6. In at least one embodiment, get attributes API 2602 returns adetermined attribute 2614 using return value 2616 to a calling processusing integer value, or using a Boolean value, or using an enumeratedvalue, or using a flag, or using a signal, or using a semaphore, orusing an event, or using a combination of these and/or other such returnvalue types including, but not limited to, those described herein.

FIG. 27 illustrates an example diagram 2700 where threads of a blockcluster are waiting on other threads to perform a barrier instruction,in accordance with at least one embodiment. In at least one embodiment,a first thread 2706 of a thread block 2704 of a block cluster 2702 isbeing performed and first thread 2706 has not reached a barrierinstruction 2708, as described herein. In at least one embodiment, asecond thread 2710 of thread block 2704 of block cluster 2702 is waitingand second thread 2710 has reached barrier instruction 2708, asdescribed herein. In at least one embodiment, second thread 2710 iswaiting because second thread 2710 has performed barrier instruction2708.

In at least one embodiment, a third thread 2714 of a thread block 2712of block cluster 2702 is waiting and third thread 2714 has reachedbarrier instruction 2708, as described herein. In at least oneembodiment, third thread 2714 is waiting because third thread 2714 hasperformed barrier instruction 2708. In at least one embodiment, a fourththread 2716 of thread block 2712 of block cluster 2702 is waiting andfourth thread 2716 has reached barrier instruction 2708, as describedherein. In at least one embodiment, fourth thread 2716 is waitingbecause fourth thread 2716 has performed barrier instruction 2708.

FIG. 28 illustrates an example diagram 2800 where threads of a blockcluster have performed a barrier instruction, in accordance with atleast one embodiment. In at least one embodiment, threads illustrated inexample diagram 2800 are identical to threads illustrated in examplediagram 2700 where example diagram 2800 follows after first thread 2806has arrived at barrier instruction 2808. In at least one embodiment, afirst thread 2806 (which is first thread 2706 of example diagram 2700)of a thread block 2804 (e.g., thread block 2704 of example diagram 2700)of a block cluster 2802 (e.g., block cluster 2702 of example diagram2700) has reached a barrier instruction 2808 (e.g., barrier instruction2708 of example diagram 2700). In at least one embodiment, first thread2806 is waiting because first thread 2806 has performed barrierinstruction 2808. In at least one embodiment, a second thread 2810(e.g., second thread 2710 of example diagram 2700) of thread block 2804of block cluster 2802 is waiting, as described herein.

In at least one embodiment, a third thread 2814 (e.g., third thread 2714of example diagram 2700) of a thread block 2812 (e.g., thread block 2712of example diagram 2700) of block cluster 2802 is waiting, as describedherein. In at least one embodiment, a fourth thread 2816 (e.g., fourththread 2716 of example diagram 2700) of thread block 2812 of blockcluster 2802 is waiting, as described herein.

FIG. 29 illustrates an example diagram 2900 where threads of a blockcluster resume after performing a barrier instruction, in accordancewith at least one embodiment. In at least one embodiment, threadsillustrated in example diagram 2800 are identical to threads illustratedin example diagram 2800 where example diagram 2800 follows after firstthread 2906 has arrived at barrier instruction 2908 and all threads haveresumed execution. In at least one embodiment, all threads illustratedin example diagram 2900 have resumed as all threads illustrated inexample diagram 2900 have performed barrier instruction 2908 and maythus resume execution.

In at least one embodiment, a first thread 2906 (which is first thread2806 of example diagram 2800) of a thread block 2904 (e.g., thread block2804 of example diagram 2800) of a block cluster 2902 (e.g., blockcluster 2802 of example diagram 2800) has reached a barrier instruction2908 (e.g., barrier instruction 2808 of example diagram 2800) and hasresumed execution beyond barrier instruction 2908. In at least oneembodiment, a second thread 2910 (e.g., second thread 2810 of examplediagram 2800) of thread block 2904 is has resumed execution beyondbarrier instruction 2908, a third thread 2914 (e.g., third thread 2814of example diagram 2800) of a thread block 2912 (e.g., thread block 2812of example diagram 2800) has resumed execution beyond barrierinstruction 2908, and a fourth thread 2916 (e.g., fourth thread 2818 ofexample diagram 2800) of thread block 2912 has resumed execution beyondbarrier instruction 2908.

FIG. 30 illustrates an example application programming interface 3000 todetermine if threads of a block cluster have performed a barrierinstruction, in accordance with at least one embodiment. In at least oneembodiment, example application programming interface 3000 to determineif threads of a block cluster have performed a barrier instruction is akernel barrier arrive API 3002. In at least one embodiment, an API suchas kernel barrier arrive API 3002 is performed by a processor, such asthose described herein. In at least one embodiment, an API such askernel barrier arrive API 3002 is performed as one or more steps of acomputer-implemented method, as described herein. In at least oneembodiment, an API such as kernel barrier arrive API 3002 is performedby one or more processors of a computer system, as described herein. Inat least one embodiment, an API such as kernel barrier arrive API 3002is stored as instructions on a machine-readable medium, which can beperformed using one or more processors, as described herein. In at leastone embodiment, an API such as kernel barrier arrive API 3002, whenperformed, is to indicate whether one or more threads within two or moreblocks of threads have performed a barrier instruction.

In at least one embodiment, kernel barrier arrive API 3002 is an API toindicate whether one or more threads within two or more blocks ofthreads have performed a barrier instruction. In at least oneembodiment, kernel barrier arrive API 3002 is an API to indicate arrivalat a barrier instruction of a cluster of one or more groups ofinstructions. In at least one embodiment, kernel barrier arrive API 3002is an API to manage synchronization of one or more threads of blockclusters, as described herein at least in connection with FIGS. 27-29 .In at least one embodiment, kernel barrier arrive API 3002 receives oneor more parameters including, but not limited to, a calling thread ID3004. In at least one embodiment, kernel barrier arrive API 3002 returnsa return value 3014.

In at least one embodiment, calling thread ID 3004 of kernel barrierarrive API 3002 is an identifier of a thread that executes or otherwiseperforms one or more commands to perform kernel barrier arrive API 3002.In at least one embodiment, not shown in FIG. 30 , kernel barrier arriveAPI 3002 receives one or more additional parameters and/or of flags thatspecify how calling thread ID 3004 will be used to determine if threadsof a block cluster have performed a barrier instruction. In at least oneembodiment, when additional parameters and/or of flags that specify howcalling thread ID 3004 will be used to determine if threads of a blockcluster have performed a barrier instruction are not received, one ormore default parameters and/or flags may be used by kernel barrierarrive API 3002 to determine if threads of a block cluster haveperformed a barrier instruction, using systems and methods such as thosedescribed herein.

In at least one embodiment, kernel barrier arrive API 3002 causes aprocessor such as those described herein to execute one or more commandsto identify 3006 a thread, thread block, block cluster, and/or computegroup of a calling thread identified by calling thread ID 3004,determine 3008 whether a barrier instruction has been reached by acalling thread identified by calling thread ID 3004, and determine 3010whether to wait or proceed with thread execution based, at least inpart, on determining whether a barrier instruction has been reached by acalling thread identified by calling thread ID 3004. In at least oneembodiment, a determination of whether a barrier instruction has beenreached by a calling thread identified by calling thread ID 3004 may bea determination of whether a barrier instruction has not been reach by acalling thread identified by calling thread ID 3004. In at least oneembodiment, for example, kernel barrier arrive API 3002 may determine3008 that no threads, including a calling thread identified by callingthread ID 3004, have reached a barrier instruction. In at least oneembodiment, kernel barrier arrive API 3002 causes a processor such asthose described herein to execute one or more commands to report abarrier arrival status 3012 based, at least in part, on determiningwhether a barrier instruction has been reached by a calling threadidentified by calling thread ID 3004.

In at least one embodiment, kernel barrier arrive API 3002 reportsbarrier arrival status 3012 using return value 3014. In at least oneembodiment, kernel barrier arrive API 3002 reports barrier arrivalstatus 3012 using return value 3014 to a calling process such as exampleprocess 600 described herein at least in connection with FIG. 6 . In atleast one embodiment, kernel barrier arrive API 3002 reports barrierarrival status 3012 using return value 3014 to a calling process usinginteger value, or using a Boolean value, or using an enumerated value,or using a flag, or using a signal, or using a semaphore, or using anevent, or using a combination of these and/or other such return valuetypes including, but not limited to, those described herein.

FIG. 31 illustrates an example application programming interface 3100 todetermine if a thread should stop until all other threads of a blockcluster have performed a barrier instruction, in accordance with atleast one embodiment. In at least one embodiment, example applicationprogramming interface 3100 to determine if a thread should stop untilall other threads of a block cluster have performed a barrierinstruction is a kernel barrier wait API 3102. In at least oneembodiment, an API such as kernel barrier wait API 3102 is performed bya processor, such as those described herein. In at least one embodiment,an API such as kernel barrier wait API 3102 is performed as one or moresteps of a computer-implemented method, as described herein. In at leastone embodiment, an API such as kernel barrier wait API 3102 is performedby one or more processors of a computer system, as described herein. Inat least one embodiment, an API such as kernel barrier wait API 3102 isstored as instructions on a machine-readable medium, which can beperformed using one or more processors, as described herein. In at leastone embodiment, an API such as kernel barrier wait API 3102, whenperformed, is to cause performance of one or more threads within a groupof blocks of threads to stop at least until all threads within the groupof blocks have performed a barrier instruction.

In at least one embodiment, kernel barrier wait API 3102 is an API tocause performance of one or more threads within a group of blocks ofthreads to stop at least until all threads within the group of blockshave performed a barrier instruction. In at least one embodiment, kernelbarrier wait API 3102 is an API to cause one or more first instructionsto be prevented from being performed until a cluster of one or moregroups of instructions have performed one or more second instructions.In at least one embodiment, kernel barrier wait API 3102 is an API tomanage synchronization of one or more threads of block clusters, asdescribed herein at least in connection with FIGS. 27-29 . In at leastone embodiment, kernel barrier wait API 3102 receives one or moreparameters including, but not limited to, a calling thread ID 3104. Inat least one embodiment, kernel barrier wait API 3102 returns a returnvalue 3112.

In at least one embodiment, calling thread ID 3104 of kernel barrierwait API 3102 is an identifier of a calling thread that executes orotherwise performs one or more commands to perform kernel barrier waitAPI 3102. In at least one embodiment, not shown in FIG. 31 , kernelbarrier wait API 3102 receives one or more additional parameters and/orof flags that specify how calling thread ID 3104 will be used todetermine if a calling thread identified by calling thread ID 3104should stop until all other threads of a block cluster have performed abarrier instruction. In at least one embodiment, when additionalparameters and/or of flags that specify how calling thread ID 3104 willbe used to determine if a calling thread identified by calling thread ID3104 should stop until all other threads of a block cluster haveperformed a barrier instruction are not received, one or more defaultparameters and/or flags may be used by kernel barrier wait API 3102 todetermine if a thread should stop until all other threads of a blockcluster have performed a barrier instruction, using systems and methodssuch as those described herein.

In at least one embodiment, kernel barrier wait API 3102 causes aprocessor such as those described herein to execute one or more commandsto identify 3106 a thread, thread block, block cluster, and/or computegroup of a calling thread identified by calling thread ID 3104 anddetermine 3108 whether a barrier instruction has been reached one ormore other threads associated with a block cluster of a calling threadidentified by calling thread ID 3104. In at least one embodiment, adetermination of whether a barrier instruction has been reached one ormore other threads associated with a block cluster of a calling threadidentified by calling thread ID 3104 may be a determination of whether abarrier instruction has not been reached one or more other threadsassociated with a block cluster of a calling thread identified bycalling thread ID 3104. In at least one embodiment, for example, kernelbarrier wait API 3102 may determine 3108 that no threads, including acalling thread identified by calling thread ID 3104, have reached abarrier instruction. In at least one embodiment, kernel barrier wait API3102 causes a processor such as those described herein to execute one ormore commands to report a determination of whether a calling threadidentified by calling thread ID 3104 should wait or proceed 3110 based,at least in part, on whether a barrier instruction has been reached oneor more other threads associated with a block cluster of a callingthread identified by calling thread ID 3104.

In at least one embodiment, kernel barrier wait API 3102 returns adetermination whether to wait or proceed 3110 using return value 3112.In at least one embodiment, kernel barrier wait API 3102 returnsdetermination whether to wait or proceed 3110 using return value 3112 toa calling process such as example process 600 described herein at leastin connection with FIG. 6 . In at least one embodiment, kernel barrierwait API 3102 returns determination whether to wait or proceed 3110using return value 3112 to a calling process using integer value, orusing a Boolean value, or using an enumerated value, or using a flag, orusing a signal, or using a semaphore, or using an event, or using acombination of these and/or other such return value types including, butnot limited to, those described herein.

FIG. 32 illustrates an example application programming interface 3200 todetermine if threads of a block cluster have performed a barrierinstruction and to stop until all other threads of a block cluster haveperformed a barrier instruction, in accordance with at least oneembodiment. In at least one embodiment, example application programminginterface 3200 to determine if threads of a block cluster have performeda barrier instruction and to stop until all other threads of a blockcluster have performed a barrier instruction is a kernel barrier syncAPI 3202. In at least one embodiment, an API such as kernel barrier syncAPI 3202 is performed by a processor, such as those described herein. Inat least one embodiment, an API such as kernel barrier sync API 3202 isperformed as one or more steps of a computer-implemented method, asdescribed herein. In at least one embodiment, an API such as kernelbarrier sync API 3202 is performed by one or more processors of acomputer system, as described herein. In at least one embodiment, an APIsuch as kernel barrier sync API 3202 is stored as instructions on amachine-readable medium, which can be performed using one or moreprocessors, as described herein. In at least one embodiment, an API suchas kernel barrier sync API 3202, when performed, is to indicate whetherone or more threads within a group of blocks of threads have performed abarrier instruction and to cause performance of one or more threadswithin the group of blocks of threads to stop at least until all threadswithin the group of blocks have performed the barrier instruction.

In at least one embodiment, kernel barrier sync API 3202 is an API toindicate whether one or more threads within two or more blocks ofthreads have performed a barrier instruction and to cause performance ofone or more threads within the group of blocks of threads to stop atleast until all threads within the group of blocks have performed thebarrier instruction. In at least one embodiment, kernel barrier sync API3202 is an API to cause one or more first instructions to be preventedfrom being performed until a cluster of one or more groups ofinstructions have performed one or more second instructions. In at leastone embodiment, kernel barrier synch API 3202 is an API to managesynchronization of one or more threads of block clusters, as describedherein at least in connection with FIGS. 27-29 . In at least oneembodiment, kernel barrier sync API 3202 receives one or more parametersincluding, but not limited to, a calling thread ID 3204. In at least oneembodiment, kernel barrier sync API 3202 returns a return value 3218.

In at least one embodiment, calling thread ID 3204 of kernel barriersync API 3202 is an identifier of a calling thread that executes orotherwise performs one or more commands to perform kernel barrier syncAPI 3202. In at least one embodiment, not shown in FIG. 32 , kernelbarrier sync API 3202 receives one or more additional parameters and/orof flags that specify how calling thread ID 3204 will be used todetermine if threads of a block cluster have performed a barrierinstruction and to stop until all other threads of a block cluster haveperformed a barrier instruction. In at least one embodiment, whenadditional parameters and/or of flags that specify how calling thread ID3204 will be used to determine if threads of a block cluster haveperformed a barrier instruction and to stop until all other threads of ablock cluster have performed a barrier instruction are not received, oneor more default parameters and/or flags may be used by kernel barriersync API 3202 to determine if threads of a block cluster have performeda barrier instruction and to stop until all other threads of a blockcluster have performed a barrier instruction, using systems and methodssuch as those described herein.

In at least one embodiment, kernel barrier sync API 3202 causes aprocessor such as those described herein to execute one or more commandsto identify 3206 a thread, thread block, block cluster, and/or computegroup of a calling thread identified by calling thread ID 3204,determine 3208 whether a barrier instruction has been reached by acalling thread identified by calling thread ID 3204 and determine 3210whether to wait or proceed with thread execution based, at least inpart, on determining whether a barrier instruction has been reached by acalling thread identified by calling thread ID 3204. In at least oneembodiment, as described herein, a determination of whether a barrierinstruction has been reached by a calling thread identified by callingthread ID 3204 may be a determination that a barrier instruction has notbeen reached by a calling thread identified by calling thread ID 3204 ora determination that no threads have reached a barrier instruction.

In at least one embodiment, kernel barrier sync API 3202 causes aprocessor such as those described herein to execute one or more commandsto determine 3212 whether a barrier instruction has been reached one ormore other threads associated with a block cluster of a calling threadidentified by calling thread ID 3204 and determine 3214 whether to waitor proceed with thread execution based, at least in part, on whether abarrier instruction has been reached one or more other threadsassociated with a block cluster of a calling thread identified bycalling thread ID 3204. In at least one embodiment, a determination ofwhether to wait or proceed with thread execution based, at least inpart, on determining whether a barrier instruction has been reached by acalling thread identified by calling thread ID 3204 may be combined witha determination of whether to wait or proceed with thread executionbased, at least in part, on whether a barrier instruction has beenreached one or more other threads associated with a block cluster of acalling thread identified by calling thread ID 3204. In at least oneembodiment, kernel barrier sync API 3202 causes a processor such asthose described herein to execute one or more commands to report abarrier arrival status 3216 based, at least in part, on determiningwhether a barrier instruction has been reached by a calling threadidentified by calling thread ID 3204.

In at least one embodiment, kernel barrier sync API 3202 returns barrierarrival status 3216 using return value 3218. In at least one embodiment,kernel barrier sync API 3202 returns barrier arrival status 3216 usingreturn value 3218 to a calling process such as example process 600described herein at least in connection with FIG. 6 . In at least oneembodiment, kernel barrier sync API 3202 returns barrier arrival status3216 using return value 3218 to a calling process using integer value,or using a Boolean value, or using an enumerated value, or using a flag,or using a signal, or using a semaphore, or using an event, or using acombination of these and/or other such return value types including, butnot limited to, those described herein.

FIG. 33 illustrates an example diagram 3300 where shared memory of acompute unit is mapped between threads of a block cluster, in accordancewith at least one embodiment. In at least one embodiment, a blockcluster 3306 of a compute unit 3302 has thread block 3308 and threadblock 3318, as described herein. In at least one embodiment, sharedmemory 3304 includes thread memory 3314 of a thread 3310 of thread block3308 and thread memory 3316 of a thread 3312 of thread block 3308. In atleast one embodiment, shared memory 3304 also includes thread memory3322 of thread 3320 of thread block 3318.

In at least one embodiment, a thread such as thread 3320 causesexecution of one or more commands to execute an API such as map sharedmemory API 3402, described herein at least in connection with FIG. 34 tomap 3324 thread memory 3316 of thread 3312 to thread 3320 so that thread3320 can access thread memory 3316. In at least one embodiment, thread3320 executes or otherwise performs one or more commands to map 3324thread memory 3316 read-only, so that thread 3320 can read from threadmemory 3316 but cannot write to thread memory 3316. In at least oneembodiment, thread 3320 executes or otherwise performs one or morecommands to map 3324 thread memory 3316 as writable, so that thread 3320can write to thread memory 3316.

In at least one embodiment, not shown in FIG. 33 , a thread such asthread 3320 is part of a first thread block of a first block cluster ofa first compute unit of a graphics processor such as those describedherein and thread memory 3316 of thread 3312 is of a second (e.g.,different) compute unit of a graphics processor so that thread 3320accesses thread memory in shared memory of a different compute unit. Inat least one embodiment, not shown in FIG. 33 , a thread such as thread3320 is part of a first thread block of a first block cluster of a firstcompute unit of a first graphics processor such as those describedherein and thread memory 3316 of thread 3312 is of a different computeunit of a second (e.g., different) graphics processor so that thread3320 accesses thread memory in shared memory of a different compute unitof a different graphics processor, as described herein.

FIG. 34 illustrates an example application programming interface 3400 tomap memory between threads of a block cluster, in accordance with atleast one embodiment. In at least one embodiment, example applicationprogramming interface 3400 to map memory between threads of a blockcluster is a map shared memory API 3402. In at least one embodiment, anAPI such as map shared memory API 3402 is performed by a processor, suchas those described herein. In at least one embodiment, an API such asmap shared memory API 3402 is performed as one or more steps of acomputer-implemented method, as described herein. In at least oneembodiment, an API such as map shared memory API 3402 is performed byone or more processors of a computer system, as described herein. In atleast one embodiment, an API such as map shared memory API 3402 isstored as instructions on a machine-readable medium, which can beperformed using one or more processors, as described herein. In at leastone embodiment, an API such as map shared memory API 3402], whenperformed, is to cause memory to be shared between two or more groups ofblocks of threads.

In at least one embodiment, map shared memory API 3402 is an API tocause memory to be shared between two or more groups of blocks ofthreads. In at least one embodiment, map shared memory API 3402 is anAPI to cause one or more memory locations of first cluster of one ormore groups of instructions to be accessible to a second cluster of oneor more groups of instructions. In at least one embodiment, map sharedmemory API 3402 is an API to map thread memory between threads of ablock cluster, as described herein at least in connection with FIG. 33 .In at least one embodiment, map shared memory API 3402 receives one ormore parameters including, but not limited to, a calling thread 3404, amemory address 3406, and/or a block rank 3408. In at least oneembodiment, map shared memory API 3402 returns a return value 3418.

In at least one embodiment, calling thread 3404 of map shared memory API3402 is an identifier of a thread that executes or otherwise performsone or more commands to perform map shared memory API 3402. In at leastone embodiment, memory address 3406 is a memory address that is used togenerate a translated memory address. In at least one embodiment, blockrank 3408 is a rank of a block within a block cluster that is determinedas described herein.

In at least one embodiment, not shown in FIG. 34 , map shared memory API3402 receives one or more additional parameters and/or of flags thatspecify how calling thread 3404, memory address 3406, and/or block rank3408 will be used to map memory between threads of a block cluster. Inat least one embodiment, when additional parameters and/or of flags thatspecify how calling thread 3404, memory address 3406, and/or block rank3408 will be used to map memory between threads of a block cluster arenot received, one or more default parameters and/or flags may be used bymap shared memory API 3402 to map memory between threads of a blockcluster, using systems and methods such as those described herein.

In at least one embodiment, map shared memory API 3402 causes aprocessor such as those described herein to execute one or more commandsto identify 3410 a thread, thread block, block cluster, and/or computegroup of calling thread 3404, translate 3412 memory address 3406 basedat least in part on a thread block, block cluster, and/or compute groupof calling thread 3404 and/or based at least in part on block rank 3408.In at least one embodiment, map shared memory API 3402 causes aprocessor such as those described herein to execute one or more commandsto store 3414 and/or to return 3416 a translated address to that callingthread 3404 can map memory using a translated address. In at least oneembodiment, map shared memory API 3402 returns a translated addressusing return value 3418. In at least one embodiment, not shown in FIG.34 , map shared memory API 3402 returns success and/or failure asdescribed herein.

In at least one embodiment, map shared memory API 3402 returns atranslated address using return value 3418 to a calling process such asexample process 600 described herein at least in connection with FIG. 6. In at least one embodiment, map shared memory API 3402 returns atranslated address using return value 3418 to a calling process usinginteger value, or using a Boolean value, or using an enumerated value,or using a flag, or using a signal, or using a semaphore, or using anevent, or using a combination of these and/or other such return valuetypes including, but not limited to, those described herein.

FIG. 35 illustrates an example software stack 3500 where applicationprogramming interface calls associated with block clusters areprocessed, in accordance with at least one embodiment. In at least oneembodiment, example software stack 3500 is at least a part of a softwarestack such as those described herein. In at least one embodiment, anapplication 3502 executes a command to determine if a feature 3504 issupported. In at least one embodiment, an application 3502 executes acommand to determine if feature 3504 to perform an API such as thosedescribed herein is supported.

In at least one embodiment, application 3502 uses 3506 one or moreruntime APIs 3508 to determine if feature 3504 is supported. In at leastone embodiment, runtime APIs 3508 use 3510 one or more driver APIs 3512to determine if feature 3504 is supported. In at least one embodiment,not shown in FIG. 35 , application 3502 uses one or more driver APIs3512 to determine if feature 3504 is supported. In at least oneembodiment, driver APIs 3512 query 3514 computer system hardware 3516 todetermine if feature 3504 is supported.

In at least one embodiment, computer system hardware 3516 determines iffeature 3504 is supported by a processor 3534, by querying a set ofcapabilities associated with processor 3534. In at least one embodiment,processor 3534 is a processor such as processor 102, described herein atleast in connection with FIG. 1 . In at least one embodiment, computersystem hardware 3516 determines if a feature 3504 is supported byprocessor 3534, using an operating system of processor 3534. In at leastone embodiment, computer system hardware 3516 determines if feature issupported by a graphics processor 3536 by querying a set of capabilitiesassociated with graphics processor 3536. In at least one embodiment,graphics processor 3536 is a graphics processor such as graphicsprocessor 108, described herein at least in connection with FIG. 1 . Inat least one embodiment, computer system hardware 3516 determines iffeature 3504 is supported by graphics processor 3536 using an operatingsystem of processor 3534. In at least one embodiment, computer systemhardware 3516 determines if feature 3504 is supported by graphicsprocessor 3536, using an operating system of graphics processor 3536.

In at least one embodiment, after computer system hardware 3516determines whether feature 3504 is supported, computer system hardware3516 returns 3518 a determination result using driver APIs 3512, whichmay return 3520 a determination result using runtime APIs 3508, whichmay return 3522 a determination result to application 3502. In at leastone embodiment, if application 3502 receives a determination result thatindicates that feature 3504 is supported 3524, application 3502 performsa feature 3526 using one or more APIs such as those described herein atleast in connection with FIGS. 7-34 (e.g., set block cluster dimensionAPI 802, get cluster dimension API 902, set scheduling policy API 1202,get scheduling policy API 1302, number of blocks supported API 1502,indicate cluster parameters API 1702, maximum cluster size supported API1902, launch kernel with block clusters API 2102, get attributes API2602, kernel barrier arrive API 3002, kernel barrier wait API 3102,kernel barrier sync API 3202, and/or map shared memory API 3402). In atleast one embodiment, application 3502 performs feature 3526 usingsystems and methods such as those described herein.

In at least one embodiment, application 3502 performs feature 3526 using3528 runtime APIs 3508 including, but not limited to, runtime versionsof APIs such as those described herein at least in connection with FIGS.7-34 (e.g., set block cluster dimension API 802, get cluster dimensionAPI 902, set scheduling policy API 1202, get scheduling policy API 1302,number of blocks supported API 1502, indicate cluster parameters API1702, maximum cluster size supported API 1902, launch kernel with blockclusters API 2102, get attributes API 2602, kernel barrier arrive API3002, kernel barrier wait API 3102, kernel barrier sync API 3202, and/ormap shared memory API 3402).

In at least one embodiment, runtime APIs 3508 perform feature 3526 using3530 driver APIs 3512 including, but not limited to, driver versions ofAPIs such as those described herein at least in connection with FIGS.7-34 (e.g., set block cluster dimension API 802, get cluster dimensionAPI 902, set scheduling policy API 1202, get scheduling policy API 1302,number of blocks supported API 1502, indicate cluster parameters API1702, maximum cluster size supported API 1902, launch kernel with blockclusters API 2102, get attributes API 2602, kernel barrier arrive API3002, kernel barrier wait API 3102, kernel barrier sync API 3202, and/ormap shared memory API 3402). In at least one embodiment, not shown inFIG. 35 , application 3502 performs feature 3526 using 3530 driver APIs3512. In at least one embodiment, driver APIs 3512 perform feature 3526using 3532 computer system hardware 3516.

In the following description, numerous specific details are set forth toprovide a more thorough understanding of at least one embodiment.However, it will be apparent to one skilled in the art that theinventive concepts may be practiced without one or more of thesespecific details.

Data Center

FIG. 36 illustrates an exemplary data center 3600, in accordance with atleast one embodiment. In at least one embodiment, data center 3600includes, without limitation, a data center infrastructure layer 3610, aframework layer 3620, a software layer 3630 and an application layer3640.

In at least one embodiment, as shown in FIG. 36 , data centerinfrastructure layer 3610 may include a resource orchestrator 3612,grouped computing resources 3614, and node computing resources (“nodeC.R.s”) 3616(1)-3616(N), where “N” represents any whole, positiveinteger. In at least one embodiment, node C.R.s 3616(1)-3616(N) mayinclude, but are not limited to, any number of central processing units(“CPUs”) or other processors (including accelerators, field programmablegate arrays (“FPGAs”), data processing units (“DPUs”) in networkdevices, graphics processors, etc.), memory devices (e.g., dynamicread-only memory), storage devices (e.g., solid state or disk drives),network input/output (“NW I/O”) devices, network switches, virtualmachines (“VMs”), power modules, and cooling modules, etc. In at leastone embodiment, one or more node C.R.s from among node C.R.s3616(1)-3616(N) may be a server having one or more of above-mentionedcomputing resources.

In at least one embodiment, grouped computing resources 3614 may includeseparate groupings of node C.R.s housed within one or more racks (notshown), or many racks housed in data centers at various geographicallocations (also not shown). Separate groupings of node C.R.s withingrouped computing resources 3614 may include grouped compute, network,memory or storage resources that may be configured or allocated tosupport one or more workloads. In at least one embodiment, several nodeC.R.s including CPUs or processors may grouped within one or more racksto provide compute resources to support one or more workloads. In atleast one embodiment, one or more racks may also include any number ofpower modules, cooling modules, and network switches, in anycombination.

In at least one embodiment, resource orchestrator 3612 may configure orotherwise control one or more node C.R.s 3616(1)-3616(N) and/or groupedcomputing resources 3614. In at least one embodiment, resourceorchestrator 3612 may include a software design infrastructure (“SDI”)management entity for data center 3600. In at least one embodiment,resource orchestrator 3612 may include hardware, software or somecombination thereof.

In at least one embodiment, as shown in FIG. 36 , framework layer 3620includes, without limitation, a job scheduler 3632, a configurationmanager 3634, a resource manager 3636 and a distributed file system3638. In at least one embodiment, framework layer 3620 may include aframework to support software 3652 of software layer 3630 and/or one ormore application(s) 3642 of application layer 3640. In at least oneembodiment, software 3652 or application(s) 3642 may respectivelyinclude web-based service software or applications, such as thoseprovided by Amazon Web Services, Google Cloud and Microsoft Azure. In atleast one embodiment, framework layer 3620 may be, but is not limitedto, a type of free and open-source software web application frameworksuch as Apache Spark™ (hereinafter “Spark”) that may utilize distributedfile system 3638 for large-scale data processing (e.g., “big data”). Inat least one embodiment, job scheduler 3632 may include a Spark driverto facilitate scheduling of workloads supported by various layers ofdata center 3600. In at least one embodiment, configuration manager 3634may be capable of configuring different layers such as software layer3630 and framework layer 3620, including Spark and distributed filesystem 3638 for supporting large-scale data processing. In at least oneembodiment, resource manager 3636 may be capable of managing clusteredor grouped computing resources mapped to or allocated for support ofdistributed file system 3638 and job scheduler 3632. In at least oneembodiment, clustered or grouped computing resources may include groupedcomputing resource 3614 at data center infrastructure layer 3610. In atleast one embodiment, resource manager 3636 may coordinate with resourceorchestrator 3612 to manage these mapped or allocated computingresources.

In at least one embodiment, software 3652 included in software layer3630 may include software used by at least portions of node C.R.s3616(1)-3616(N), grouped computing resources 3614, and/or distributedfile system 3638 of framework layer 3620. One or more types of softwaremay include, but are not limited to, Internet web page search software,e-mail virus scan software, database software, and streaming videocontent software.

In at least one embodiment, application(s) 3642 included in applicationlayer 3640 may include one or more types of applications used by atleast portions of node C.R.s 3616(1)-3616(N), grouped computingresources 3614, and/or distributed file system 3638 of framework layer3620. In at least one or more types of applications may include, withoutlimitation, CUDA applications.

In at least one embodiment, any of configuration manager 3634, resourcemanager 3636, and resource orchestrator 3612 may implement any numberand type of self-modifying actions based on any amount and type of dataacquired in any technically feasible fashion. In at least oneembodiment, self-modifying actions may relieve a data center operator ofdata center 3600 from making possibly bad configuration decisions andpossibly avoiding underutilized and/or poor performing portions of adata center.

In at least one embodiment, at least one component shown or describedwith respect to FIG. 36 is used to implement techniques and/or functionsdescribed in connection with FIGS. 1-35 . In at least one embodiment, atleast one of grouped computing resources 3614 and node C.R. 3616(1-N) isused to perform an application programming interface to indicate two ormore blocks of threads to be scheduled in parallel. In at least oneembodiment, at least one of grouped computing resources 3614 and nodeC.R. 3616(1-N) is used to perform an application programming interfaceto determine which of two or more blocks of threads to be scheduled inparallel. In at least one embodiment, at least one of grouped computingresources 3614 and node C.R. 3616(1-N) is used to perform an applicationprogramming interface comprising one or more parameters to cause ascheduling policy of one or more blocks of one or more threads to beperformed. In at least one embodiment, at least one of grouped computingresources 3614 and node C.R. 3616(1-N) is used to perform an applicationprogramming interface comprising one or more parameters to indicate ascheduling policy of one or more blocks of one or more threads. In atleast one embodiment, at least one of grouped computing resources 3614and node C.R. 3616(1-N) is used to perform an application programminginterface to indicate a maximum number of blocks of threads capable ofbeing scheduled in parallel. In at least one embodiment, at least one ofgrouped computing resources 3614 and node C.R. 3616(1-N) is used toperform an application programming interface comprising one or moreparameters to indicate one or more attributes of one or more groups ofblocks of one or more threads. In at least one embodiment, at least oneof grouped computing resources 3614 and node C.R. 3616(1-N) is used toperform an application programming interface to indicate a maximumnumber of blocks of threads to be scheduled in parallel. In at least oneembodiment, at least one of grouped computing resources 3614 and nodeC.R. 3616(1-N) is used to perform an application programming interfaceto cause a kernel to be generated to cause two or more blocks of two ormore threads to be scheduled in parallel. In at least one embodiment, atleast one of grouped computing resources 3614 and node C.R. 3616(1-N) isused to perform an application programming interface comprising one ormore parameters to indicate one or more limitations of one or moreattributes of one or more groups of blocks of one or more threads. In atleast one embodiment, at least one of grouped computing resources 3614and node C.R. 3616(1-N) is used to perform an application programminginterface to indicate whether one or more threads within two or moreblocks of threads have performed a barrier instruction. In at least oneembodiment, at least one of grouped computing resources 3614 and nodeC.R. 3616(1-N) is used to perform an application programming interfaceto cause performance of one or more threads within a group of blocks ofthreads to stop at least until all threads within the group of blockshave performed a barrier instruction. In at least one embodiment, atleast one of grouped computing resources 3614 and node C.R. 3616(1-N) isused to perform an application programming interface to indicate whetherone or more threads within two or more blocks of threads have performeda barrier instruction and to cause performance of one or more threadswithin the group of blocks of threads to stop at least until all threadswithin the group of blocks have performed the barrier instruction. In atleast one embodiment, at least one of grouped computing resources 3614and node C.R. 3616(1-N) is used to perform an application programminginterface to cause memory to be shared between two or more groups ofblocks of threads. In at least one embodiment, at least one of groupedcomputing resources 3614 and node C.R. 3616(1-N) is used to perform atleast one aspect described with respect to example computer system 100,example diagram 200, diagram 200, example diagram 300, example diagram400, example diagram 500, example process 600, example diagram 700,example application programming interface 800, example applicationprogramming interface 900, example diagram 1000, example diagram 1100,example application programming interface 1200, example applicationprogramming interface 1300, example computer system 1400, exampleapplication programming interface 1500, example diagram 1600, exampleapplication programming interface 1700, example computer system 1800,example application programming interface 1900, example computer system2000, example application programming interface 2100, example diagram2200, example diagram 2300, example diagram 2400, example diagram 2500,example application programming interface 2600, example diagram 2700,example diagram 2800, example diagram 2900, example applicationprogramming interface 3000, example application programming interface3100, example application programming interface 3200, example diagram3300, example application programming interface 3400, example softwarestack 3500, and/or other systems, methods, or operations describedherein.

Computer-Based Systems

The following figures set forth, without limitation, exemplarycomputer-based systems that can be used to implement at least oneembodiment.

FIG. 37 illustrates a processing system 3700, in accordance with atleast one embodiment. In at least one embodiment, processing system 3700includes one or more processors 3702 and one or more graphics processors3708, and may be a single processor desktop system, a multiprocessorworkstation system, or a server system having a large number ofprocessors 3702 or processor cores 3707. In at least one embodiment,processing system 3700 is a processing platform incorporated within asystem-on-a-chip (“SoC”) integrated circuit for use in mobile, handheld,or embedded devices.

In at least one embodiment, processing system 3700 can include, or beincorporated within a server-based gaming platform, a game console, amedia console, a mobile gaming console, a handheld game console, or anonline game console. In at least one embodiment, processing system 3700is a mobile phone, smart phone, tablet computing device or mobileInternet device. In at least one embodiment, processing system 3700 canalso include, couple with, or be integrated within a wearable device,such as a smart watch wearable device, smart eyewear device, augmentedreality device, or virtual reality device. In at least one embodiment,processing system 3700 is a television or set top box device having oneor more processors 3702 and a graphical interface generated by one ormore graphics processors 3708.

In at least one embodiment, one or more processors 3702 each include oneor more processor cores 3707 to process instructions which, whenexecuted, perform operations for system and user software. In at leastone embodiment, each of one or more processor cores 3707 is configuredto process a specific instruction set 3709. In at least one embodiment,instruction set 3709 may facilitate Complex Instruction Set Computing(“CISC”), Reduced Instruction Set Computing (“RISC”), or computing via aVery Long Instruction Word (“VLIW”). In at least one embodiment,processor cores 3707 may each process a different instruction set 3709,which may include instructions to facilitate emulation of otherinstruction sets. In at least one embodiment, processor core 3707 mayalso include other processing devices, such as a digital signalprocessor (“DSP”).

In at least one embodiment, processor 3702 includes cache memory(‘cache”) 3704. In at least one embodiment, processor 3702 can have asingle internal cache or multiple levels of internal cache. In at leastone embodiment, cache memory is shared among various components ofprocessor 3702. In at least one embodiment, processor 3702 also uses anexternal cache (e.g., a Level 3 (“L3”) cache or Last Level Cache(“LLC”)) (not shown), which may be shared among processor cores 3707using known cache coherency techniques. In at least one embodiment,register file 3706 is additionally included in processor 3702 which mayinclude different types of registers for storing different types of data(e.g., integer registers, floating point registers, status registers,and an instruction pointer register). In at least one embodiment,register file 3706 may include general-purpose registers or otherregisters.

In at least one embodiment, one or more processor(s) 3702 are coupledwith one or more interface bus(es) 3710 to transmit communicationsignals such as address, data, or control signals between processor 3702and other components in processing system 3700. In at least oneembodiment interface bus 3710, in one embodiment, can be a processorbus, such as a version of a Direct Media Interface (“DMI”) bus. In atleast one embodiment, interface bus 3710 is not limited to a DMI bus,and may include one or more Peripheral Component Interconnect buses(e.g., “PCI,” PCI Express (“PCIe”)), memory buses, or other types ofinterface buses. In at least one embodiment processor(s) 3702 include anintegrated memory controller 3716 and a platform controller hub 3730. Inat least one embodiment, memory controller 3716 facilitatescommunication between a memory device and other components of processingsystem 3700, while platform controller hub (“PCH”) 3730 providesconnections to Input/Output (“I/O”) devices via a local I/O bus.

In at least one embodiment, memory device 3720 can be a dynamic randomaccess memory (“DRAM”) device, a static random access memory (“SRAM”)device, flash memory device, phase-change memory device, or some othermemory device having suitable performance to serve as processor memory.In at least one embodiment memory device 3720 can operate as systemmemory for processing system 3700, to store data 3722 and instructions3721 for use when one or more processors 3702 executes an application orprocess. In at least one embodiment, memory controller 3716 also coupleswith an optional external graphics processor 3712, which may communicatewith one or more graphics processors 3708 in processors 3702 to performgraphics and media operations. In at least one embodiment, a displaydevice 3711 can connect to processor(s) 3702. In at least one embodimentdisplay device 3711 can include one or more of an internal displaydevice, as in a mobile electronic device or a laptop device or anexternal display device attached via a display interface (e.g.,DisplayPort, etc.). In at least one embodiment, display device 3711 caninclude a head mounted display (“HMD”) such as a stereoscopic displaydevice for use in virtual reality (“VR”) applications or augmentedreality (“AR”) applications.

In at least one embodiment, platform controller hub 3730 enablesperipherals to connect to memory device 3720 and processor 3702 via ahigh-speed I/O bus. In at least one embodiment, I/O peripherals include,but are not limited to, an audio controller 3746, a network controller3734, a firmware interface 3728, a wireless transceiver 3726, touchsensors 3725, a data storage device 3724 (e.g., hard disk drive, flashmemory, etc.). In at least one embodiment, data storage device 3724 canconnect via a storage interface (e.g., SATA) or via a peripheral bus,such as PCI, or PCIe. In at least one embodiment, touch sensors 3725 caninclude touch screen sensors, pressure sensors, or fingerprint sensors.In at least one embodiment, wireless transceiver 3726 can be a Wi-Fitransceiver, a Bluetooth transceiver, or a mobile network transceiversuch as a 3G, 4G, or Long Term Evolution (“LTE”) transceiver. In atleast one embodiment, firmware interface 3728 enables communication withsystem firmware, and can be, for example, a unified extensible firmwareinterface (“UEFI”). In at least one embodiment, network controller 3734can enable a network connection to a wired network. In at least oneembodiment, a high-performance network controller (not shown) coupleswith interface bus 3710. In at least one embodiment, audio controller3746 is a multi-channel high definition audio controller. In at leastone embodiment, processing system 3700 includes an optional legacy I/Ocontroller 3740 for coupling legacy (e.g., Personal System 2 (“PS/2”))devices to processing system 3700. In at least one embodiment, platformcontroller hub 3730 can also connect to one or more Universal Serial Bus(“USB”) controllers 3742 connect input devices, such as keyboard andmouse 3743 combinations, a camera 3744, or other USB input devices.

In at least one embodiment, an instance of memory controller 3716 andplatform controller hub 3730 may be integrated into a discreet externalgraphics processor, such as external graphics processor 3712. In atleast one embodiment, platform controller hub 3730 and/or memorycontroller 3716 may be external to one or more processor(s) 3702. Forexample, in at least one embodiment, processing system 3700 can includean external memory controller 3716 and platform controller hub 3730,which may be configured as a memory controller hub and peripheralcontroller hub within a system chipset that is in communication withprocessor(s) 3702.

In at least one embodiment, at least one component shown or describedwith respect to FIG. 37 is used to implement techniques and/or functionsdescribed in connection with FIGS. 1-35 . In at least one embodiment, atleast one of processor(s) 3702 or external graphics processor 3712 isused to perform an application programming interface to indicate two ormore blocks of threads to be scheduled in parallel. In at least oneembodiment, at least one of processor(s) 3702 or external graphicsprocessor 3712 is used to perform an application programming interfaceto determine which of two or more blocks of threads to be scheduled inparallel. In at least one embodiment, at least one of processor(s) 3702or external graphics processor 3712 is used to perform an applicationprogramming interface comprising one or more parameters to cause ascheduling policy of one or more blocks of one or more threads to beperformed. In at least one embodiment, at least one of processor(s) 3702or external graphics processor 3712 is used to perform an applicationprogramming interface comprising one or more parameters to indicate ascheduling policy of one or more blocks of one or more threads. In atleast one embodiment, at least one of processor(s) 3702 or externalgraphics processor 3712 is used to perform an application programminginterface to indicate a maximum number of blocks of threads capable ofbeing scheduled in parallel. In at least one embodiment, at least one ofprocessor(s) 3702 or external graphics processor 3712 is used to performan application programming interface comprising one or more parametersto indicate one or more attributes of one or more groups of blocks ofone or more threads. In at least one embodiment, at least one ofprocessor(s) 3702 or external graphics processor 3712 is used to performan application programming interface to indicate a maximum number ofblocks of threads to be scheduled in parallel. In at least oneembodiment, at least one of processor(s) 3702 or external graphicsprocessor 3712 is used to perform an application programming interfaceto cause a kernel to be generated to cause two or more blocks of two ormore threads to be scheduled in parallel. In at least one embodiment, atleast one of processor(s) 3702 or external graphics processor 3712 isused to perform an application programming interface comprising one ormore parameters to indicate one or more limitations of one or moreattributes of one or more groups of blocks of one or more threads. In atleast one embodiment, at least one of processor(s) 3702 or externalgraphics processor 3712 is used to perform an application programminginterface to indicate whether one or more threads within two or moreblocks of threads have performed a barrier instruction. In at least oneembodiment, at least one of processor(s) 3702 or external graphicsprocessor 3712 is used to perform an application programming interfaceto cause performance of one or more threads within a group of blocks ofthreads to stop at least until all threads within the group of blockshave performed a barrier instruction. In at least one embodiment, atleast one of processor(s) 3702 or external graphics processor 3712 isused to perform an application programming interface to indicate whetherone or more threads within two or more blocks of threads have performeda barrier instruction and to cause performance of one or more threadswithin the group of blocks of threads to stop at least until all threadswithin the group of blocks have performed the barrier instruction. In atleast one embodiment, at least one of processor(s) 3702 or externalgraphics processor 3712 is used to perform an application programminginterface to cause memory to be shared between two or more groups ofblocks of threads.

In at least one embodiment, at least one of processor(s) 3702 orexternal graphics processor 3712 is used to perform at least one aspectdescribed with respect to example computer system 100, example diagram200, diagram 200, example diagram 300, example diagram 400, examplediagram 500, example process 600, example diagram 700, exampleapplication programming interface 800, example application programminginterface 900, example diagram 1000, example diagram 1100, exampleapplication programming interface 1200, example application programminginterface 1300, example computer system 1400, example applicationprogramming interface 1500, example diagram 1600, example applicationprogramming interface 1700, example computer system 1800, exampleapplication programming interface 1900, example computer system 2000,example application programming interface 2100, example diagram 2200,example diagram 2300, example diagram 2400, example diagram 2500,example application programming interface 2600, example diagram 2700,example diagram 2800, example diagram 2900, example applicationprogramming interface 3000, example application programming interface3100, example application programming interface 3200, example diagram3300, example application programming interface 3400, example softwarestack 3500, and/or other systems, methods, or operations describedherein.

FIG. 38 illustrates a computer system 3800, in accordance with at leastone embodiment. In at least one embodiment, computer system 3800 may bea system with interconnected devices and components, an SOC, or somecombination. In at least on embodiment, computer system 3800 is formedwith a processor 3802 that may include execution units to execute aninstruction. In at least one embodiment, computer system 3800 mayinclude, without limitation, a component, such as processor 3802 toemploy execution units including logic to perform algorithms forprocessing data. In at least one embodiment, computer system 3800 mayinclude processors, such as PENTIUM® Processor family, Xeon™, Itanium®,XScale™ and/or StrongARM™, Intel® Core™, or Intel® Nervana™microprocessors available from Intel Corporation of Santa Clara,California, although other systems (including PCs having othermicroprocessors, engineering workstations, set-top boxes and like) mayalso be used. In at least one embodiment, computer system 3800 mayexecute a version of WINDOWS' operating system available from MicrosoftCorporation of Redmond, Wash., although other operating systems (UNIXand Linux for example), embedded software, and/or graphical userinterfaces, may also be used.

In at least one embodiment, computer system 3800 may be used in otherdevices such as handheld devices and embedded applications. Someexamples of handheld devices include cellular phones, Internet Protocoldevices, digital cameras, personal digital assistants (“PDAs”), andhandheld PCs. In at least one embodiment, embedded applications mayinclude a microcontroller, a digital signal processor (DSP), an SoC,network computers (“NetPCs”), set-top boxes, network hubs, wide areanetwork (“WAN”) switches, or any other system that may perform one ormore instructions.

In at least one embodiment, computer system 3800 may include, withoutlimitation, processor 3802 that may include, without limitation, one ormore execution units 3808 that may be configured to execute a ComputeUnified Device Architecture (“CUDA”) (CUDA® is developed by NVIDIACorporation of Santa Clara, CA) program. In at least one embodiment, aCUDA program is at least a portion of a software application written ina CUDA programming language. In at least one embodiment, computer system3800 is a single processor desktop or server system. In at least oneembodiment, computer system 3800 may be a multiprocessor system. In atleast one embodiment, processor 3802 may include, without limitation, aCISC microprocessor, a RISC microprocessor, a VLIW microprocessor, aprocessor implementing a combination of instruction sets, or any otherprocessor device, such as a digital signal processor, for example. In atleast one embodiment, processor 3802 may be coupled to a processor bus3810 that may transmit data signals between processor 3802 and othercomponents in computer system 3800.

In at least one embodiment, processor 3802 may include, withoutlimitation, a Level 1 (“L1”) internal cache memory (“cache”) 3804. In atleast one embodiment, processor 3802 may have a single internal cache ormultiple levels of internal cache. In at least one embodiment, cachememory may reside external to processor 3802. In at least oneembodiment, processor 3802 may also include a combination of bothinternal and external caches. In at least one embodiment, a registerfile 3806 may store different types of data in various registersincluding, without limitation, integer registers, floating pointregisters, status registers, and instruction pointer register.

In at least one embodiment, execution unit 3808, including, withoutlimitation, logic to perform integer and floating point operations, alsoresides in processor 3802. Processor 3802 may also include a microcode(“ucode”) read only memory (“ROM”) that stores microcode for certainmacro instructions. In at least one embodiment, execution unit 3808 mayinclude logic to handle a packed instruction set 3809. In at least oneembodiment, by including packed instruction set 3809 in an instructionset of a general-purpose processor 3802, along with associated circuitryto execute instructions, operations used by many multimedia applicationsmay be performed using packed data in a general-purpose processor 3802.In at least one embodiment, many multimedia applications may beaccelerated and executed more efficiently by using full width of aprocessor's data bus for performing operations on packed data, which mayeliminate a need to transfer smaller units of data across a processor'sdata bus to perform one or more operations one data element at a time.

In at least one embodiment, execution unit 3808 may also be used inmicrocontrollers, embedded processors, graphics devices, DSPs, and othertypes of logic circuits. In at least one embodiment, computer system3800 may include, without limitation, a memory 3820. In at least oneembodiment, memory 3820 may be implemented as a DRAM device, an SRAMdevice, flash memory device, or other memory device. Memory 3820 maystore instruction(s) 3819 and/or data 3821 represented by data signalsthat may be executed by processor 3802.

In at least one embodiment, a system logic chip may be coupled toprocessor bus 3810 and memory 3820. In at least one embodiment, thesystem logic chip may include, without limitation, a memory controllerhub (“MCH”) 3816, and processor 3802 may communicate with MCH 3816 viaprocessor bus 3810. In at least one embodiment, MCH 3816 may provide ahigh bandwidth memory path 3818 to memory 3820 for instruction and datastorage and for storage of graphics commands, data and textures. In atleast one embodiment, MCH 3816 may direct data signals between processor3802, memory 3820, and other components in computer system 3800 and tobridge data signals between processor bus 3810, memory 3820, and asystem I/O 3822. In at least one embodiment, system logic chip mayprovide a graphics port for coupling to a graphics controller. In atleast one embodiment, MCH 3816 may be coupled to memory 3820 throughhigh bandwidth memory path 3818 and graphics/video card 3812 may becoupled to MCH 3816 through an Accelerated Graphics Port (“AGP”)interconnect 3814.

In at least one embodiment, computer system 3800 may use system I/O 3822that is a proprietary hub interface bus to couple MCH 3816 to I/Ocontroller hub (“ICH”) 3830. In at least one embodiment, ICH 3830 mayprovide direct connections to some I/O devices via a local I/O bus. Inat least one embodiment, local I/O bus may include, without limitation,a high-speed I/O bus for connecting peripherals to memory 3820, achipset, and processor 3802. Examples may include, without limitation,an audio controller 3829, a firmware hub (“flash BIOS”) 3828, a wirelesstransceiver 3826, a data storage 3824, a legacy I/O controller 3823containing a user input interface 3825 and a keyboard interface, aserial expansion port 3827, such as a USB, and a network controller3834. Data storage 3824 may comprise a hard disk drive, a floppy diskdrive, a CD-ROM device, a flash memory device, or other mass storagedevice.

In at least one embodiment, FIG. 38 illustrates a system, which includesinterconnected hardware devices or “chips.” In at least one embodiment,FIG. 38 may illustrate an exemplary SoC. In at least one embodiment,devices illustrated in FIG. 38 may be interconnected with proprietaryinterconnects, standardized interconnects (e.g., PCIe), or somecombination thereof. In at least one embodiment, one or more componentsof system 3800 are interconnected using compute express link (“CXL”)interconnects.

In at least one embodiment, at least one component shown or describedwith respect to FIG. 38 is used to implement techniques and/or functionsdescribed in connection with FIGS. 1-35 . In at least one embodiment,processor 3802 is used to perform an application programming interfaceto indicate two or more blocks of threads to be scheduled in parallel.In at least one embodiment, processor 3802 is used to perform anapplication programming interface to determine which of two or moreblocks of threads to be scheduled in parallel. In at least oneembodiment, processor 3802 is used to perform an application programminginterface comprising one or more parameters to cause a scheduling policyof one or more blocks of one or more threads to be performed. In atleast one embodiment, processor 3802 is used to perform an applicationprogramming interface comprising one or more parameters to indicate ascheduling policy of one or more blocks of one or more threads. In atleast one embodiment, processor 3802 is used to perform an applicationprogramming interface to indicate a maximum number of blocks of threadscapable of being scheduled in parallel. In at least one embodiment,processor 3802 is used to perform an application programming interfacecomprising one or more parameters to indicate one or more attributes ofone or more groups of blocks of one or more threads. In at least oneembodiment, processor 3802 is used to perform an application programminginterface to indicate a maximum number of blocks of threads to bescheduled in parallel. In at least one embodiment, processor 3802 isused to perform an application programming interface to cause a kernelto be generated to cause two or more blocks of two or more threads to bescheduled in parallel. In at least one embodiment, processor 3802 isused to perform an application programming interface comprising one ormore parameters to indicate one or more limitations of one or moreattributes of one or more groups of blocks of one or more threads. In atleast one embodiment, processor 3802 is used to perform an applicationprogramming interface to indicate whether one or more threads within twoor more blocks of threads have performed a barrier instruction. In atleast one embodiment, processor 3802 is used to perform an applicationprogramming interface to cause performance of one or more threads withina group of blocks of threads to stop at least until all threads withinthe group of blocks have performed a barrier instruction. In at leastone embodiment, processor 3802 is used to perform an applicationprogramming interface to indicate whether one or more threads within twoor more blocks of threads have performed a barrier instruction and tocause performance of one or more threads within the group of blocks ofthreads to stop at least until all threads within the group of blockshave performed the barrier instruction. In at least one embodiment,processor 3802 is used to perform an application programming interfaceto cause memory to be shared between two or more groups of blocks ofthreads.

In at least one embodiment, processor 3802 is used to perform at leastone aspect described with respect to example computer system 100,example diagram 200, diagram 200, example diagram 300, example diagram400, example diagram 500, example process 600, example diagram 700,example application programming interface 800, example applicationprogramming interface 900, example diagram 1000, example diagram 1100,example application programming interface 1200, example applicationprogramming interface 1300, example computer system 1400, exampleapplication programming interface 1500, example diagram 1600, exampleapplication programming interface 1700, example computer system 1800,example application programming interface 1900, example computer system2000, example application programming interface 2100, example diagram2200, example diagram 2300, example diagram 2400, example diagram 2500,example application programming interface 2600, example diagram 2700,example diagram 2800, example diagram 2900, example applicationprogramming interface 3000, example application programming interface3100, example application programming interface 3200, example diagram3300, example application programming interface 3400, example softwarestack 3500, and/or other systems, methods, or operations describedherein.

FIG. 39 illustrates a system 3900, in accordance with at least oneembodiment. In at least one embodiment, system 3900 is an electronicdevice that utilizes a processor 3910. In at least one embodiment,system 3900 may be, for example and without limitation, a notebook, atower server, a rack server, a blade server, an edge devicecommunicatively coupled to one or more on-premise or cloud serviceproviders, a laptop, a desktop, a tablet, a mobile device, a phone, anembedded computer, or any other suitable electronic device.

In at least one embodiment, system 3900 may include, without limitation,processor 3910 communicatively coupled to any suitable number or kind ofcomponents, peripherals, modules, or devices. In at least oneembodiment, processor 3910 is coupled using a bus or interface, such asan I²C bus, a System Management Bus (“SMBus”), a Low Pin Count (“LPC”)bus, a Serial Peripheral Interface (“SPI”), a High Definition Audio(“HDA”) bus, a Serial Advance Technology Attachment (“SATA”) bus, a USB(versions 1, 2, 3), or a Universal Asynchronous Receiver/Transmitter(“UART”) bus. In at least one embodiment, FIG. 39 illustrates a systemwhich includes interconnected hardware devices or “chips.” In at leastone embodiment, FIG. 39 may illustrate an exemplary SoC. In at least oneembodiment, devices illustrated in FIG. 39 may be interconnected withproprietary interconnects, standardized interconnects (e.g., PCIe) orsome combination thereof. In at least one embodiment, one or morecomponents of FIG. 39 are interconnected using CXL interconnects.

In at least one embodiment, FIG. 39 may include a display 3924, a touchscreen 3925, a touch pad 3930, a Near Field Communications unit (“NFC”)3945, a sensor hub 3940, a thermal sensor 3946, an Express Chipset(“EC”) 3935, a Trusted Platform Module (“TPM”) 3938, BIOS/firmware/flashmemory (“BIOS, FW Flash”) 3922, a DSP 3960, a Solid State Disk (“SSD”)or Hard Disk Drive (“HDD”) 3920, a wireless local area network unit(“WLAN”) 3950, a Bluetooth unit 3952, a Wireless Wide Area Network unit(“WWAN”) 3956, a Global Positioning System (“GPS”) 3955, a camera (“USB3.0 camera”) 3954 such as a USB 3.0 camera, or a Low Power Double DataRate (“LPDDR”) memory unit (“LPDDR3”) 3915 implemented in, for example,LPDDR3 standard. These components may each be implemented in anysuitable manner.

In at least one embodiment, other components may be communicativelycoupled to processor 3910 through components discussed above. In atleast one embodiment, an accelerometer 3941, an Ambient Light Sensor(“ALS”) 3942, a compass 3943, and a gyroscope 3944 may becommunicatively coupled to sensor hub 3940. In at least one embodiment,a thermal sensor 3939, a fan 3937, a keyboard 3936, and a touch pad 3930may be communicatively coupled to EC 3935. In at least one embodiment, aspeaker 3963, a headphones 3964, and a microphone (“mic”) 3965 may becommunicatively coupled to an audio unit (“audio codec and class d amp”)3962, which may in turn be communicatively coupled to DSP 3960. In atleast one embodiment, audio unit 3962 may include, for example andwithout limitation, an audio coder/decoder (“codec”) and a class Damplifier. In at least one embodiment, a SIM card (“SIM”) 3957 may becommunicatively coupled to WWAN unit 3956. In at least one embodiment,components such as WLAN unit 3950 and Bluetooth unit 3952, as well asWWAN unit 3956 may be implemented in a Next Generation Form Factor(“NGFF”).

In at least one embodiment, at least one component shown or describedwith respect to FIG. 39 is used to implement techniques and/or functionsdescribed in connection with FIGS. 1-35 . In at least one embodiment,processor 3910 is used to perform an application programming interfaceto indicate two or more blocks of threads to be scheduled in parallel.In at least one embodiment, processor 3910 is used to determine which oftwo or more blocks of threads to be scheduled in parallel. In at leastone embodiment, processor 3910 is used to perform an applicationprogramming interface comprising one or more parameters to cause ascheduling policy of one or more blocks of one or more threads to beperformed. In at least one embodiment, processor 3910 is used to performan application programming interface comprising one or more parametersto indicate a scheduling policy of one or more blocks of one or morethreads. In at least one embodiment, processor 3910 is used to performan application programming interface to indicate a maximum number ofblocks of threads capable of being scheduled in parallel. In at leastone embodiment, processor 3910 is used to perform an applicationprogramming interface comprising one or more parameters to indicate oneor more attributes of one or more groups of blocks of one or morethreads. In at least one embodiment, processor 3910 is used to performan application programming interface to indicate a maximum number ofblocks of threads to be scheduled in parallel. In at least oneembodiment, processor 3910 is used to perform an application programminginterface to cause a kernel to be generated to cause two or more blocksof two or more threads to be scheduled in parallel. In at least oneembodiment, processor 3910 is used to perform an application programminginterface comprising one or more parameters to indicate one or morelimitations of one or more attributes of one or more groups of blocks ofone or more threads. In at least one embodiment, processor 3910 is usedto perform an application programming interface to indicate whether oneor more threads within two or more blocks of threads have performed abarrier instruction. In at least one embodiment, processor 3910 is usedto perform an application programming interface to cause performance ofone or more threads within a group of blocks of threads to stop at leastuntil all threads within the group of blocks have performed a barrierinstruction. In at least one embodiment, processor 3910 is used toperform an application programming interface to indicate whether one ormore threads within two or more blocks of threads have performed abarrier instruction and to cause performance of one or more threadswithin the group of blocks of threads to stop at least until all threadswithin the group of blocks have performed the barrier instruction. In atleast one embodiment, processor 3910 is used to perform an applicationprogramming interface to cause memory to be shared between two or moregroups of blocks of threads.

In at least one embodiment, processor 3910 is used to perform at leastone aspect described with respect to example computer system 100,example diagram 200, example diagram 300, example diagram 400, examplediagram 500, example process 600, example diagram 700, exampleapplication programming interface 800, example application programminginterface 900, example diagram 1000, example diagram 1100, exampleapplication programming interface 1200, example application programminginterface 1300, example computer system 1400, example applicationprogramming interface 1500, example diagram 1600, example applicationprogramming interface 1700, example computer system 1800, exampleapplication programming interface 1900, example computer system 2000,example application programming interface 2100, example diagram 2200,example diagram 2300, example diagram 2400, example diagram 2500,example application programming interface 2600, example diagram 2700,example diagram 2800, example diagram 2900, example applicationprogramming interface 3000, example application programming interface3100, example application programming interface 3200, example diagram3300, example application programming interface 3400, example softwarestack 3500, and/or other systems, methods, or operations describedherein.

FIG. 40 illustrates an exemplary integrated circuit 4000, in accordancewith at least one embodiment. In at least one embodiment, exemplaryintegrated circuit 4000 is an SoC that may be fabricated using one ormore IP cores. In at least one embodiment, integrated circuit 4000includes one or more application processor(s) 4005 (e.g., CPUs, DPUs),at least one graphics processor 4010, and may additionally include animage processor 4015 and/or a video processor 4020, any of which may bea modular IP core. In at least one embodiment, integrated circuit 4000includes peripheral or bus logic including a USB controller 4025, a UARTcontroller 4030, an SPI/SDIO controller 4035, and an I²S/I²C controller4040. In at least one embodiment, integrated circuit 4000 can include adisplay device 4045 coupled to one or more of a high-definitionmultimedia interface (“HDMI”) controller 4050 and a mobile industryprocessor interface (“MIPI”) display interface 4055. In at least oneembodiment, storage may be provided by a flash memory subsystem 4060including flash memory and a flash memory controller. In at least oneembodiment, a memory interface may be provided via a memory controller4065 for access to SDRAM or SRAM memory devices. In at least oneembodiment, some integrated circuits additionally include an embeddedsecurity engine 4070.

In at least one embodiment, at least one component shown or describedwith respect to FIG. 40 is used to implement techniques and/or functionsdescribed in connection with FIGS. 1-35 . In at least one embodiment, atleast one of application processor 40 05, graphics processor 40 imageprocessor 40 15, or video processor 40 20 is used to perform anapplication programming interface to indicate two or more blocks ofthreads to be scheduled in parallel. In at least one embodiment, atleast one of application processor 40 05, graphics processor 40 10,image processor 40 15, or video processor 40 20 is used to perform anapplication programming interface to determine which of two or moreblocks of threads to be scheduled in parallel. In at least oneembodiment, at least one of application processor 40 05, graphicsprocessor 40 10, image processor 40 15, or video processor 40 20 is usedto perform an application programming interface comprising one or moreparameters to cause a scheduling policy of one or more blocks of one ormore threads to be performed. In at least one embodiment, at least oneof application processor 40 05, graphics processor 40 10, imageprocessor 40 15, or video processor 40 20 is used to perform anapplication programming interface comprising one or more parameters toindicate a scheduling policy of one or more blocks of one or morethreads. In at least one embodiment, at least one of applicationprocessor 40 05, graphics processor 40 10, image processor 40 15, orvideo processor 40 20 is used to perform an application programminginterface to indicate a maximum number of blocks of threads capable ofbeing scheduled in parallel. In at least one embodiment, at least one ofapplication processor 40 05, graphics processor 40 10, image processor40 15, or video processor 40 20 is used to perform an applicationprogramming interface comprising one or more parameters to indicate oneor more attributes of one or more groups of blocks of one or morethreads. In at least one embodiment, at least one of applicationprocessor 40 05, graphics processor 40 10, image processor 40 15, orvideo processor 40 20 is used to perform an application programminginterface to indicate a maximum number of blocks of threads to bescheduled in parallel. In at least one embodiment, at least one ofapplication processor 40 05, graphics processor 40 10, image processor40 15, or video processor 40 20 is used to perform an applicationprogramming interface to cause a kernel to be generated to cause two ormore blocks of two or more threads to be scheduled in parallel. In atleast one embodiment, at least one of application processor 40 05,graphics processor 40 10, image processor 40 15, or video processor 4020 is used to perform an application programming interface comprisingone or more parameters to indicate one or more limitations of one ormore attributes of one or more groups of blocks of one or more threads.In at least one embodiment, at least one of application processor 40 05,graphics processor 40 10, image processor 40 15, or video processor 4020 is used to perform an application programming interface to indicatewhether one or more threads within two or more blocks of threads haveperformed a barrier instruction. In at least one embodiment, at leastone of application processor 40 05, graphics processor 40 10, imageprocessor 40 15, or video processor 40 20 is used to perform anapplication programming interface to cause performance of one or morethreads within a group of blocks of threads to stop at least until allthreads within the group of blocks have performed a barrier instruction.In at least one embodiment, at least one of application processor 40 05,graphics processor 40 10, image processor 40 15, or video processor 4020 is used to perform an application programming interface to indicatewhether one or more threads within two or more blocks of threads haveperformed a barrier instruction and to cause performance of one or morethreads within the group of blocks of threads to stop at least until allthreads within the group of blocks have performed the barrierinstruction. In at least one embodiment, at least one of applicationprocessor 40 05, graphics processor 40 10, image processor 40 15, orvideo processor 40 20 is used to perform an application programminginterface to cause memory to be shared between two or more groups ofblocks of threads.

In at least one embodiment, at least one of application processor 40 05,graphics processor 40 10, image processor 40 15, or video processor 4020 is used to perform at least one aspect described with respect toexample computer system 100, example diagram 200, example diagram 300,example diagram 400, example diagram 500, example process 600, examplediagram 700, example application programming interface 800, exampleapplication programming interface 900, example diagram 1000, examplediagram 1100, example application programming interface 1200, exampleapplication programming interface 1300, example computer system 1400,example application programming interface 1500, example diagram 1600,example application programming interface 1700, example computer system1800, example application programming interface 1900, example computersystem 2000, example application programming interface 2100, examplediagram 2200, example diagram 2300, example diagram 2400, examplediagram 2500, example application programming interface 2600, examplediagram 2700, example diagram 2800, example diagram 2900, exampleapplication programming interface 3000, example application programminginterface 3100, example application programming interface 3200, examplediagram 3300, example application programming interface 3400, examplesoftware stack 3500, and/or other systems, methods, or operationsdescribed herein.

FIG. 41 illustrates a computing system 4100, according to at least oneembodiment; In at least one embodiment, computing system 4100 includes aprocessing subsystem 4101 having one or more processor(s) 4102 and asystem memory 4104 communicating via an interconnection path that mayinclude a memory hub 4105. In at least one embodiment, memory hub 4105may be a separate component within a chipset component or may beintegrated within one or more processor(s) 4102. In at least oneembodiment, memory hub 4105 couples with an I/O subsystem 4111 via acommunication link 4106. In at least one embodiment, I/O subsystem 4111includes an I/O hub 4107 that can enable computing system 4100 toreceive input from one or more input device(s) 4108. In at least oneembodiment, I/O hub 4107 can enable a display controller, which may beincluded in one or more processor(s) 4102, to provide outputs to one ormore display device(s) 4110A. In at least one embodiment, one or moredisplay device(s) 4110A coupled with I/O hub 4107 can include a local,internal, or embedded display device.

In at least one embodiment, processing subsystem 4101 includes one ormore parallel processor(s) 4112 coupled to memory hub 4105 via a bus orother communication link 4113. In at least one embodiment, communicationlink 4113 may be one of any number of standards based communication linktechnologies or protocols, such as, but not limited to PCIe, or may be avendor specific communications interface or communications fabric. In atleast one embodiment, one or more parallel processor(s) 4112 form acomputationally focused parallel or vector processing system that caninclude a large number of processing cores and/or processing clusters,such as a many integrated core processor. In at least one embodiment,one or more parallel processor(s) 4112 form a graphics processingsubsystem that can output pixels to one of one or more display device(s)4110A coupled via I/O Hub 4107. In at least one embodiment, one or moreparallel processor(s) 4112 can also include a display controller anddisplay interface (not shown) to enable a direct connection to one ormore display device(s) 4110B.

In at least one embodiment, a system storage unit 4114 can connect toI/O hub 4107 to provide a storage mechanism for computing system 4100.In at least one embodiment, an I/O switch 4116 can be used to provide aninterface mechanism to enable connections between I/O hub 4107 and othercomponents, such as a network adapter 4118 and/or wireless networkadapter 4119 that may be integrated into a platform, and various otherdevices that can be added via one or more add-in device(s) 4120. In atleast one embodiment, network adapter 4118 can be an Ethernet adapter oranother wired network adapter. In at least one embodiment, wirelessnetwork adapter 4119 can include one or more of a Wi-Fi, Bluetooth, NFC,or other network device that includes one or more wireless radios.

In at least one embodiment, computing system 4100 can include othercomponents not explicitly shown, including USB or other portconnections, optical storage drives, video capture devices, and thelike, that may also be connected to I/O hub 4107. In at least oneembodiment, communication paths interconnecting various components inFIG. 41 may be implemented using any suitable protocols, such as PCIbased protocols (e.g., PCIe), or other bus or point-to-pointcommunication interfaces and/or protocol(s), such as NVLink high-speedinterconnect, or interconnect protocols.

In at least one embodiment, one or more parallel processor(s) 4112incorporate circuitry optimized for graphics and video processing,including, for example, video output circuitry, and constitutes agraphics processing unit (“GPU”). In at least one embodiment, one ormore parallel processor(s) 4112 incorporate circuitry optimized forgeneral purpose processing. In at least embodiment, components ofcomputing system 4100 may be integrated with one or more other systemelements on a single integrated circuit. For example, in at least oneembodiment, one or more parallel processor(s) 4112, memory hub 4105,processor(s) 4102, and I/O hub 4107 can be integrated into an SoCintegrated circuit. In at least one embodiment, components of computingsystem 4100 can be integrated into a single package to form a system inpackage (“SIP”) configuration. In at least one embodiment, at least aportion of the components of computing system 4100 can be integratedinto a multi-chip module (“MCM”), which can be interconnected with othermulti-chip modules into a modular computing system. In at least oneembodiment, I/O subsystem 4111 and display devices 4110B are omittedfrom computing system 4100.

In at least one embodiment, at least one component shown or describedwith respect to FIG. 41 is used to implement techniques and/or functionsdescribed in connection with FIGS. 1-35 . In at least one embodiment, atleast one of processor(s) 4102 or parallel processor(s) 4112 is used toperform an application programming interface to indicate two or moreblocks of threads to be scheduled in parallel. In at least oneembodiment, at least one of processor(s) 4102 or parallel processor(s)4112 is used to perform an application programming interface todetermine which of two or more blocks of threads to be scheduled inparallel. In at least one embodiment, at least one of processor(s) 4102or parallel processor(s) 4112 is used to perform an applicationprogramming interface comprising one or more parameters to cause ascheduling policy of one or more blocks of one or more threads to beperformed. In at least one embodiment, at least one of processor(s) 4102or parallel processor(s) 4112 is used to perform an applicationprogramming interface comprising one or more parameters to indicate ascheduling policy of one or more blocks of one or more threads. In atleast one embodiment, at least one of processor(s) 4102 or parallelprocessor(s) 4112 is used to perform an application programminginterface to indicate a maximum number of blocks of threads capable ofbeing scheduled in parallel. In at least one embodiment, at least one ofprocessor(s) 4102 or parallel processor(s) 4112 is used to perform anapplication programming interface comprising one or more parameters toindicate one or more attributes of one or more groups of blocks of oneor more threads. In at least one embodiment, at least one ofprocessor(s) 4102 or parallel processor(s) 4112 is used to perform anapplication programming interface to indicate a maximum number of blocksof threads to be scheduled in parallel. In at least one embodiment, atleast one of processor(s) 4102 or parallel processor(s) 4112 is used toperform an application programming interface to cause a kernel to begenerated to cause two or more blocks of two or more threads to bescheduled in parallel. In at least one embodiment, at least one ofprocessor(s) 4102 or parallel processor(s) 4112 is used to perform anapplication programming interface comprising one or more parameters toindicate one or more limitations of one or more attributes of one ormore groups of blocks of one or more threads. In at least oneembodiment, at least one of processor(s) 4102 or parallel processor(s)4112 is used to perform an application programming interface to indicatewhether one or more threads within two or more blocks of threads haveperformed a barrier instruction. In at least one embodiment, at leastone of processor(s) 4102 or parallel processor(s) 4112 is used toperform an application programming interface to cause performance of oneor more threads within a group of blocks of threads to stop at leastuntil all threads within the group of blocks have performed a barrierinstruction. In at least one embodiment, at least one of processor(s)4102 or parallel processor(s) 4112 is used to perform an applicationprogramming interface to indicate whether one or more threads within twoor more blocks of threads have performed a barrier instruction and tocause performance of one or more threads within the group of blocks ofthreads to stop at least until all threads within the group of blockshave performed the barrier instruction. In at least one embodiment, atleast one of processor(s) 4102 or parallel processor(s) 4112 is used toperform an application programming interface to cause memory to beshared between two or more groups of blocks of threads.

In at least one embodiment, at least one of processor(s) 4102 orparallel processor(s) 4112 is used to perform at least one aspectdescribed with respect to example computer system 100, example diagram200, example diagram 300, example diagram 400, example diagram 500,example process 600, example diagram 700, example applicationprogramming interface 800, example application programming interface900, example diagram 1000, example diagram 1100, example applicationprogramming interface 1200, example application programming interface1300, example computer system 1400, example application programminginterface 1500, example diagram 1600, example application programminginterface 1700, example computer system 1800, example applicationprogramming interface 1900, example computer system 2000, exampleapplication programming interface 2100, example diagram 2200, examplediagram 2300, example diagram 2400, example diagram 2500, exampleapplication programming interface 2600, example diagram 2700, examplediagram 2800, example diagram 2900, example application programminginterface 3000, example application programming interface 3100, exampleapplication programming interface 3200, example diagram 3300, exampleapplication programming interface 3400, example software stack 3500,and/or other systems, methods, or operations described herein.

Processing Systems

The following figures set forth, without limitation, exemplaryprocessing systems that can be used to implement at least oneembodiment.

FIG. 42 illustrates an accelerated processing unit (“APU”) 4200, inaccordance with at least one embodiment. In at least one embodiment, APU4200 is developed by AN/ID Corporation of Santa Clara, CA. In at leastone embodiment, APU 4200 can be configured to execute an applicationprogram, such as a CUDA program. In at least one embodiment, APU 4200includes, without limitation, a core complex 4210, a graphics complex4240, fabric 4260, I/O interfaces 4270, memory controllers 4280, adisplay controller 4292, and a multimedia engine 4294. In at least oneembodiment, APU 4200 may include, without limitation, any number of corecomplexes 4210, any number of graphics complexes 4250, any number ofdisplay controllers 4292, and any number of multimedia engines 4294 inany combination. For explanatory purposes, multiple instances of likeobjects are denoted herein with reference numbers identifying the objectand parenthetical numbers identifying the instance where needed.

In at least one embodiment, core complex 4210 is a CPU, graphics complex4240 is a GPU, and APU 4200 is a processing unit that integrates,without limitation, 4210 and 4240 onto a single chip. In at least oneembodiment, some tasks may be assigned to core complex 4210 and othertasks may be assigned to graphics complex 4240. In at least oneembodiment, core complex 4210 is configured to execute main controlsoftware associated with APU 4200, such as an operating system. In atleast one embodiment, core complex 4210 is the master processor of APU4200, controlling and coordinating operations of other processors. In atleast one embodiment, core complex 4210 issues commands that control theoperation of graphics complex 4240. In at least one embodiment, corecomplex 4210 can be configured to execute host executable code derivedfrom CUDA source code, and graphics complex 4240 can be configured toexecute device executable code derived from CUDA source code.

In at least one embodiment, core complex 4210 includes, withoutlimitation, cores 4220(1)-4220(4) and an L3 cache 4230. In at least oneembodiment, core complex 4210 may include, without limitation, anynumber of cores 4220 and any number and type of caches in anycombination. In at least one embodiment, cores 4220 are configured toexecute instructions of a particular instruction set architecture(“ISA”). In at least one embodiment, each core 4220 is a CPU core.

In at least one embodiment, each core 4220 includes, without limitation,a fetch/decode unit 4222, an integer execution engine 4224, a floatingpoint execution engine 4226, and an L2 cache 4228. In at least oneembodiment, fetch/decode unit 4222 fetches instructions, decodes suchinstructions, generates micro-operations, and dispatches separatemicro-instructions to integer execution engine 4224 and floating pointexecution engine 4226. In at least one embodiment, fetch/decode unit4222 can concurrently dispatch one micro-instruction to integerexecution engine 4224 and another micro-instruction to floating pointexecution engine 4226. In at least one embodiment, integer executionengine 4224 executes, without limitation, integer and memory operations.In at least one embodiment, floating point engine 4226 executes, withoutlimitation, floating point and vector operations. In at least oneembodiment, fetch-decode unit 4222 dispatches micro-instructions to asingle execution engine that replaces both integer execution engine 4224and floating point execution engine 4226.

In at least one embodiment, each core 4220(i), where i is an integerrepresenting a particular instance of core 4220, may access L2 cache4228(i) included in core 4220(i). In at least one embodiment, each core4220 included in core complex 4210(j), where j is an integerrepresenting a particular instance of core complex 4210, is connected toother cores 4220 included in core complex 4210(j) via L3 cache 4230(j)included in core complex 4210(j). In at least one embodiment, cores 4220included in core complex 4210(j), where j is an integer representing aparticular instance of core complex 4210, can access all of L3 cache4230(j) included in core complex 4210(j). In at least one embodiment, L3cache 4230 may include, without limitation, any number of slices.

In at least one embodiment, graphics complex 4240 can be configured toperform compute operations in a highly-parallel fashion. In at least oneembodiment, graphics complex 4240 is configured to execute graphicspipeline operations such as draw commands, pixel operations, geometriccomputations, and other operations associated with rendering an image toa display. In at least one embodiment, graphics complex 4240 isconfigured to execute operations unrelated to graphics. In at least oneembodiment, graphics complex 4240 is configured to execute bothoperations related to graphics and operations unrelated to graphics.

In at least one embodiment, graphics complex 4240 includes, withoutlimitation, any number of compute units 4250 and an L2 cache 4242. In atleast one embodiment, compute units 4250 share L2 cache 4242. In atleast one embodiment, L2 cache 4242 is partitioned. In at least oneembodiment, graphics complex 4240 includes, without limitation, anynumber of compute units 4250 and any number (including zero) and type ofcaches. In at least one embodiment, graphics complex 4240 includes,without limitation, any amount of dedicated graphics hardware.

In at least one embodiment, each compute unit 4250 includes, withoutlimitation, any number of SIMD units 4252 and a shared memory 4254. Inat least one embodiment, each SIMD unit 4252 implements a SIMDarchitecture and is configured to perform operations in parallel. In atleast one embodiment, each compute unit 4250 may execute any number ofthread blocks, but each thread block executes on a single compute unit4250. In at least one embodiment, a thread block includes, withoutlimitation, any number of threads of execution. In at least oneembodiment, a workgroup is a thread block. In at least one embodiment,each SIMD unit 4252 executes a different warp. In at least oneembodiment, a warp is a group of threads (e.g., 16 threads), where eachthread in the warp belongs to a single thread block and is configured toprocess a different set of data based on a single set of instructions.In at least one embodiment, predication can be used to disable one ormore threads in a warp. In at least one embodiment, a lane is a thread.In at least one embodiment, a work item is a thread. In at least oneembodiment, a wavefront is a warp. In at least one embodiment, differentwavefronts in a thread block may synchronize together and communicatevia shared memory 4254.

In at least one embodiment, fabric 4260 is a system interconnect thatfacilitates data and control transmissions across core complex 4210,graphics complex 4240, I/O interfaces 4270, memory controllers 4280,display controller 4292, and multimedia engine 4294. In at least oneembodiment, APU 4200 may include, without limitation, any amount andtype of system interconnect in addition to or instead of fabric 4260that facilitates data and control transmissions across any number andtype of directly or indirectly linked components that may be internal orexternal to APU 4200. In at least one embodiment, I/O interfaces 4270are representative of any number and type of I/O interfaces (e.g., PCI,PCI-Extended (“PCI-X”), PCIe, gigabit Ethernet (“GBE”), USB, etc.). Inat least one embodiment, various types of peripheral devices are coupledto I/O interfaces 4270. In at least one embodiment, peripheral devicesthat are coupled to I/O interfaces 4270 may include, without limitation,keyboards, mice, printers, scanners, joysticks or other types of gamecontrollers, media recording devices, external storage devices, networkinterface cards, and so forth.

In at least one embodiment, display controller AMD92 displays images onone or more display device(s), such as a liquid crystal display (“LCD”)device. In at least one embodiment, multimedia engine 4294 includes,without limitation, any amount and type of circuitry that is related tomultimedia, such as a video decoder, a video encoder, an image signalprocessor, etc. In at least one embodiment, memory controllers 4280facilitate data transfers between APU 4200 and a unified system memory4290. In at least one embodiment, core complex 4210 and graphics complex4240 share unified system memory 4290.

In at least one embodiment, APU 4200 implements a memory subsystem thatincludes, without limitation, any amount and type of memory controllers4280 and memory devices (e.g., shared memory 4254) that may be dedicatedto one component or shared among multiple components. In at least oneembodiment, APU 4200 implements a cache subsystem that includes, withoutlimitation, one or more cache memories (e.g., L2 caches 4328, L3 cache4230, and L2 cache 4242) that may each be private to or shared betweenany number of components (e.g., cores 4220, core complex 4210, SIMDunits 4252, compute units 4250, and graphics complex 4240).

In at least one embodiment, at least one component shown or describedwith respect to FIG. 42 is used to implement techniques and/or functionsdescribed in connection with FIGS. 1-35 . In at least one embodiment, atleast one element of core complex 4210 or graphics complex 4240 is usedto perform an application programming interface to indicate two or moreblocks of threads to be scheduled in parallel. In at least oneembodiment, at least one element of core complex 4210 or graphicscomplex 4240 is used to perform an application programming interface todetermine which of two or more blocks of threads to be scheduled inparallel. In at least one embodiment, at least one element of corecomplex 4210 or graphics complex 4240 is used to perform an applicationprogramming interface comprising one or more parameters to cause ascheduling policy of one or more blocks of one or more threads to beperformed. In at least one embodiment, at least one element of corecomplex 4210 or graphics complex 4240 is used to perform an applicationprogramming interface comprising one or more parameters to indicate ascheduling policy of one or more blocks of one or more threads. In atleast one embodiment, at least one element of core complex 4210 orgraphics complex 4240 is used to perform an application programminginterface to indicate a maximum number of blocks of threads capable ofbeing scheduled in parallel. In at least one embodiment, at least oneelement of core complex 4210 or graphics complex 4240 is used to performan application programming interface comprising one or more parametersto indicate one or more attributes of one or more groups of blocks ofone or more threads. In at least one embodiment, at least one element ofcore complex 4210 or graphics complex 4240 is used to perform anapplication programming interface to indicate a maximum number of blocksof threads to be scheduled in parallel. In at least one embodiment, atleast one element of core complex 4210 or graphics complex 4240 is usedto perform an application programming interface to cause a kernel to begenerated to cause two or more blocks of two or more threads to bescheduled in parallel. In at least one embodiment, at least one elementof core complex 4210 or graphics complex 4240 is used to perform anapplication programming interface comprising one or more parameters toindicate one or more limitations of one or more attributes of one ormore groups of blocks of one or more threads. In at least oneembodiment, at least one element of core complex 4210 or graphicscomplex 4240 is used to perform an application programming interface toindicate whether one or more threads within two or more blocks ofthreads have performed a barrier instruction. In at least oneembodiment, at least one element of core complex 4210 or graphicscomplex 4240 is used to perform an application programming interface tocause performance of one or more threads within a group of blocks ofthreads to stop at least until all threads within the group of blockshave performed a barrier instruction. In at least one embodiment, atleast one element of core complex 4210 or graphics complex 4240 is usedto perform an application programming interface to indicate whether oneor more threads within two or more blocks of threads have performed abarrier instruction and to cause performance of one or more threadswithin the group of blocks of threads to stop at least until all threadswithin the group of blocks have performed the barrier instruction. In atleast one embodiment, at least one element of core complex 4210 orgraphics complex 4240 is used to perform an application programminginterface to cause memory to be shared between two or more groups ofblocks of threads.

In at least one embodiment, at least one element of core complex 4210 orgraphics complex 4240 is used to perform at least one aspect describedwith respect to example computer system 100, example diagram 200,example diagram 300, example diagram 400, example diagram 500, exampleprocess 600, example diagram 700, example application programminginterface 800, example application programming interface 900, examplediagram 1000, example diagram 1100, example application programminginterface 1200, example application programming interface 1300, examplecomputer system 1400, example application programming interface 1500,example diagram 1600, example application programming interface 1700,example computer system 1800, example application programming interface1900, example computer system 2000, example application programminginterface 2100, example diagram 2200, example diagram 2300, examplediagram 2400, example diagram 2500, example application programminginterface 2600, example diagram 2700, example diagram 2800, examplediagram 2900, example application programming interface 3000, exampleapplication programming interface 3100, example application programminginterface 3200, example diagram 3300, example application programminginterface 3400, example software stack 3500, and/or other systems,methods, or operations described herein.

FIG. 43 illustrates a CPU 4300, in accordance with at least oneembodiment. In at least one embodiment, CPU 4300 is developed by AMDCorporation of Santa Clara, CA. In at least one embodiment, CPU 4300 canbe configured to execute an application program. In at least oneembodiment, CPU 4300 is configured to execute main control software,such as an operating system. In at least one embodiment, CPU 4300 issuescommands that control the operation of an external GPU (not shown). Inat least one embodiment, CPU 4300 can be configured to execute hostexecutable code derived from CUDA source code, and an external GPU canbe configured to execute device executable code derived from such CUDAsource code. In at least one embodiment, CPU 4300 includes, withoutlimitation, any number of core complexes 4310, fabric 4360, I/Ointerfaces 4370, and memory controllers 4380.

In at least one embodiment, core complex 4310 includes, withoutlimitation, cores 4320(1)-4320(4) and an L3 cache 4330. In at least oneembodiment, core complex 4310 may include, without limitation, anynumber of cores 4320 and any number and type of caches in anycombination. In at least one embodiment, cores 4320 are configured toexecute instructions of a particular ISA. In at least one embodiment,each core 4320 is a CPU core.

In at least one embodiment, each core 4320 includes, without limitation,a fetch/decode unit 4322, an integer execution engine 4324, a floatingpoint execution engine 4326, and an L2 cache 4328. In at least oneembodiment, fetch/decode unit 4322 fetches instructions, decodes suchinstructions, generates micro-operations, and dispatches separatemicro-instructions to integer execution engine 4324 and floating pointexecution engine 4326. In at least one embodiment, fetch/decode unit4322 can concurrently dispatch one micro-instruction to integerexecution engine 4324 and another micro-instruction to floating pointexecution engine 4326. In at least one embodiment, integer executionengine 4324 executes, without limitation, integer and memory operations.In at least one embodiment, floating point engine 4326 executes, withoutlimitation, floating point and vector operations. In at least oneembodiment, fetch-decode unit 4322 dispatches micro-instructions to asingle execution engine that replaces both integer execution engine 4324and floating point execution engine 4326.

In at least one embodiment, each core 4320(i), where i is an integerrepresenting a particular instance of core 4320, may access L2 cache4328(i) included in core 4320(i). In at least one embodiment, each core4320 included in core complex 4310(j), where j is an integerrepresenting a particular instance of core complex 4310, is connected toother cores 4320 in core complex 4310(j) via L3 cache 4330(j) includedin core complex 4310(j). In at least one embodiment, cores 4320 includedin core complex 4310(j), where j is an integer representing a particularinstance of core complex 4310, can access all of L3 cache 4330(j)included in core complex 4310(j). In at least one embodiment, L3 cache4330 may include, without limitation, any number of slices.

In at least one embodiment, fabric 4360 is a system interconnect thatfacilitates data and control transmissions across core complexes4310(1)-4310(N) (where N is an integer greater than zero), I/Ointerfaces 4370, and memory controllers 4380. In at least oneembodiment, CPU 4300 may include, without limitation, any amount andtype of system interconnect in addition to or instead of fabric 4360that facilitates data and control transmissions across any number andtype of directly or indirectly linked components that may be internal orexternal to CPU 4300. In at least one embodiment, I/O interfaces 4370are representative of any number and type of I/O interfaces (e.g., PCI,PCI-X, PCIe, GBE, USB, etc.). In at least one embodiment, various typesof peripheral devices are coupled to I/O interfaces 4370. In at leastone embodiment, peripheral devices that are coupled to I/O interfaces4370 may include, without limitation, displays, keyboards, mice,printers, scanners, joysticks or other types of game controllers, mediarecording devices, external storage devices, network interface cards,and so forth.

In at least one embodiment, memory controllers 4380 facilitate datatransfers between CPU 4300 and a system memory 4390. In at least oneembodiment, core complex 4310 and graphics complex 4340 share systemmemory 4390. In at least one embodiment, CPU 4300 implements a memorysubsystem that includes, without limitation, any amount and type ofmemory controllers 4380 and memory devices that may be dedicated to onecomponent or shared among multiple components. In at least oneembodiment, CPU 4300 implements a cache subsystem that includes, withoutlimitation, one or more cache memories (e.g., L2 caches 4328 and L3caches 4330) that may each be private to or shared between any number ofcomponents (e.g., cores 4320 and core complexes 4310).

In at least one embodiment, at least one component shown or describedwith respect to FIG. 43 is used to implement techniques and/or functionsdescribed in connection with FIGS. 1-35 . In at least one embodiment, atleast one element of core complex 4310(1)-4310(n) is used to perform anapplication programming interface to indicate two or more blocks ofthreads to be scheduled in parallel. In at least one embodiment, atleast one element of core complex 4310(1)-4310(n) is used to perform anapplication programming interface to determine which of two or moreblocks of threads to be scheduled in parallel. In at least oneembodiment, at least one element of core complex 4310(1)-4310(n) is usedto perform an application programming interface comprising one or moreparameters to cause a scheduling policy of one or more blocks of one ormore threads to be performed. In at least one embodiment, at least oneelement of core complex 4310(1)-4310(n) is used to perform anapplication programming interface comprising one or more parameters toindicate a scheduling policy of one or more blocks of one or morethreads. In at least one embodiment, at least one element of corecomplex 4310(1)-4310(n) is used to perform an application programminginterface to indicate a maximum number of blocks of threads capable ofbeing scheduled in parallel. In at least one embodiment, at least oneelement of core complex 4310(1)-4310(n) is used to perform anapplication programming interface comprising one or more parameters toindicate one or more attributes of one or more groups of blocks of oneor more threads. In at least one embodiment, at least one element ofcore complex 4310(1)-4310(n) is used to perform an applicationprogramming interface to indicate a maximum number of blocks of threadsto be scheduled in parallel. In at least one embodiment, at least oneelement of core complex 4310(1)-4310(n) is used to perform anapplication programming interface to cause a kernel to be generated tocause two or more blocks of two or more threads to be scheduled inparallel. In at least one embodiment, at least one element of corecomplex 4310(1)-4310(n) is used to perform an application programminginterface comprising one or more parameters to indicate one or morelimitations of one or more attributes of one or more groups of blocks ofone or more threads. In at least one embodiment, at least one element ofcore complex 4310(1)-4310(n) is used to perform an applicationprogramming interface to indicate whether one or more threads within twoor more blocks of threads have performed a barrier instruction. In atleast one embodiment, at least one element of core complex4310(1)-4310(n) is used to perform an application programming interfaceto cause performance of one or more threads within a group of blocks ofthreads to stop at least until all threads within the group of blockshave performed a barrier instruction. In at least one embodiment, atleast one element of core complex 4310(1)-4310(n) is used to perform anapplication programming interface to indicate whether one or morethreads within two or more blocks of threads have performed a barrierinstruction and to cause performance of one or more threads within thegroup of blocks of threads to stop at least until all threads within thegroup of blocks have performed the barrier instruction. In at least oneembodiment, at least one element of core complex 4310(1)-4310(n) is usedto perform an application programming interface to cause memory to beshared between two or more groups of blocks of threads.

In at least one embodiment, at least one element of core complex4310(1)-4310(n) is used to perform at least one aspect described withrespect to example computer system 100, example diagram 200, examplediagram 300, example diagram 400, example diagram 500, example process600, example diagram 700, example application programming interface 800,example application programming interface 900, example diagram 1000,example diagram 1100, example application programming interface 1200,example application programming interface 1300, example computer system1400, example application programming interface 1500, example diagram1600, example application programming interface 1700, example computersystem 1800, example application programming interface 1900, examplecomputer system 2000, example application programming interface 2100,example diagram 2200, example diagram 2300, example diagram 2400,example diagram 2500, example application programming interface 2600,example diagram 2700, example diagram 2800, example diagram 2900,example application programming interface 3000, example applicationprogramming interface 3100, example application programming interface3200, example diagram 3300, example application programming interface3400, example software stack 3500, and/or other systems, methods, oroperations described herein.

FIG. 44 illustrates an exemplary accelerator integration slice 4490, inaccordance with at least one embodiment. As used herein, a “slice”comprises a specified portion of processing resources of an acceleratorintegration circuit. In at least one embodiment, the acceleratorintegration circuit provides cache management, memory access, contextmanagement, and interrupt management services on behalf of multiplegraphics processing engines included in a graphics acceleration module.The graphics processing engines may each comprise a separate GPU.Alternatively, the graphics processing engines may comprise differenttypes of graphics processing engines within a GPU such as graphicsexecution units, media processing engines (e.g., videoencoders/decoders), samplers, and blit engines. In at least oneembodiment, the graphics acceleration module may be a GPU with multiplegraphics processing engines. In at least one embodiment, the graphicsprocessing engines may be individual GPUs integrated on a commonpackage, line card, or chip.

An application effective address space 4482 within system memory 4414stores process elements 4483. In one embodiment, process elements 4483are stored in response to GPU invocations 4481 from applications 4480executed on processor 4407. A process element 4483 contains processstate for corresponding application 4480. A work descriptor (“WD”) 4484contained in process element 4483 can be a single job requested by anapplication or may contain a pointer to a queue of jobs. In at least oneembodiment, WD 4484 is a pointer to a job request queue in applicationeffective address space 4482.

Graphics acceleration module 4446 and/or individual graphics processingengines can be shared by all or a subset of processes in a system. In atleast one embodiment, an infrastructure for setting up process state andsending WD 4484 to graphics acceleration module 4446 to start a job in avirtualized environment may be included.

In at least one embodiment, a dedicated-process programming model isimplementation-specific. In this model, a single process owns graphicsacceleration module 4446 or an individual graphics processing engine.Because graphics acceleration module 4446 is owned by a single process,a hypervisor initializes an accelerator integration circuit for anowning partition and an operating system initializes acceleratorintegration circuit for an owning process when graphics accelerationmodule 4446 is assigned.

In operation, a WD fetch unit 4491 in accelerator integration slice 4490fetches next WD 4484 which includes an indication of work to be done byone or more graphics processing engines of graphics acceleration module4446. Data from WD 4484 may be stored in registers 4445 and used by amemory management unit (“MMU”) 4439, interrupt management circuit 4447and/or context management circuit 4448 as illustrated. For example, oneembodiment of MMU 4439 includes segment/page walk circuitry foraccessing segment/page tables 4486 within OS virtual address space 4485.Interrupt management circuit 4447 may process interrupt events (“INT”)4492 received from graphics acceleration module 4446. When performinggraphics operations, an effective address 4493 generated by a graphicsprocessing engine is translated to a real address by MMU 4439.

In one embodiment, a same set of registers 4445 are duplicated for eachgraphics processing engine and/or graphics acceleration module 4446 andmay be initialized by a hypervisor or operating system. Each of theseduplicated registers may be included in accelerator integration slice4490. Exemplary registers that may be initialized by a hypervisor areshown in Table 1.

TABLE 1 Hypervisor Initialized Registers 1 Slice Control Register 2 RealAddress (RA) Scheduled Processes Area Pointer 3 Authority Mask OverrideRegister 4 Interrupt Vector Table Entry Offset 5 Interrupt Vector TableEntry Limit 6 State Register 7 Logical Partition ID 8 Real address (RA)Hypervisor Accelerator Utilization Record Pointer 9 Storage DescriptionRegister

Exemplary registers that may be initialized by an operating system areshown in Table 2.

TABLE 2 Operating System Initialized Registers 1 Process and ThreadIdentification 2 Effective Address (EA) Context Save/Restore Pointer 3Virtual Address (VA) Accelerator Utilization Record Pointer 4 VirtualAddress (VA) Storage Segment Table Pointer 5 Authority Mask 6 Workdescriptor

In one embodiment, each WD 4484 is specific to a particular graphicsacceleration module 4446 and/or a particular graphics processing engine.It contains all information required by a graphics processing engine todo work or it can be a pointer to a memory location where an applicationhas set up a command queue of work to be completed.

In at least one embodiment, at least one component shown or describedwith respect to FIG. 44 is used to implement techniques and/or functionsdescribed in connection with FIGS. 1-35 . In at least one embodiment,processor 4407 is used to perform an application programming interfaceto indicate two or more blocks of threads to be scheduled in parallel.In at least one embodiment, processor 4407 is used to perform anapplication programming interface to determine which of two or moreblocks of threads to be scheduled in parallel. In at least oneembodiment, processor 4407 is used to perform an application programminginterface comprising one or more parameters to cause a scheduling policyof one or more blocks of one or more threads to be performed. In atleast one embodiment, processor 4407 is used to perform an applicationprogramming interface comprising one or more parameters to indicate ascheduling policy of one or more blocks of one or more threads. In atleast one embodiment, processor 4407 is used to perform an applicationprogramming interface to indicate a maximum number of blocks of threadscapable of being scheduled in parallel. In at least one embodiment,processor 4407 is used to perform an application programming interfacecomprising one or more parameters to indicate one or more attributes ofone or more groups of blocks of one or more threads. In at least oneembodiment, processor 4407 is used to perform an application programminginterface to indicate a maximum number of blocks of threads to bescheduled in parallel. In at least one embodiment, processor 4407 isused to perform an application programming interface to cause a kernelto be generated to cause two or more blocks of two or more threads to bescheduled in parallel. In at least one embodiment, processor 4407 isused to perform an application programming interface comprising one ormore parameters to indicate one or more limitations of one or moreattributes of one or more groups of blocks of one or more threads. In atleast one embodiment, processor 4407 is used to perform an applicationprogramming interface to indicate whether one or more threads within twoor more blocks of threads have performed a barrier instruction. In atleast one embodiment, processor 4407 is used to perform an applicationprogramming interface to cause performance of one or more threads withina group of blocks of threads to stop at least until all threads withinthe group of blocks have performed a barrier instruction. In at leastone embodiment, processor 4407 is used to perform an applicationprogramming interface to indicate whether one or more threads within twoor more blocks of threads have performed a barrier instruction and tocause performance of one or more threads within the group of blocks ofthreads to stop at least until all threads within the group of blockshave performed the barrier instruction. In at least one embodiment,processor 4407 is used to perform an application programming interfaceto cause memory to be shared between two or more groups of blocks ofthreads.

In at least one embodiment, processor 4407 is used to perform at leastone aspect described with respect to example computer system 100,example diagram 200, example diagram 300, example diagram 400, examplediagram 500, example process 600, example diagram 700, exampleapplication programming interface 800, example application programminginterface 900, example diagram 1000, example diagram 1100, exampleapplication programming interface 1200, example application programminginterface 1300, example computer system 1400, example applicationprogramming interface 1500, example diagram 1600, example applicationprogramming interface 1700, example computer system 1800, exampleapplication programming interface 1900, example computer system 2000,example application programming interface 2100, example diagram 2200,example diagram 2300, example diagram 2400, example diagram 2500,example application programming interface 2600, example diagram 2700,example diagram 2800, example diagram 2900, example applicationprogramming interface 3000, example application programming interface3100, example application programming interface 3200, example diagram3300, example application programming interface 3400, example softwarestack 3500, and/or other systems, methods, or operations describedherein.

FIGS. 45A-45B illustrate exemplary graphics processors, in accordancewith at least one embodiment. In at least one embodiment, any of theexemplary graphics processors may be fabricated using one or more IPcores. In addition to what is illustrated, other logic and circuits maybe included in at least one embodiment, including additional graphicsprocessors/cores, peripheral interface controllers, or general-purposeprocessor cores. In at least one embodiment, the exemplary graphicsprocessors are for use within an SoC.

FIG. 45A illustrates an exemplary graphics processor 4510 of an SoCintegrated circuit that may be fabricated using one or more IP cores, inaccordance with at least one embodiment. FIG. 45B illustrates anadditional exemplary graphics processor 4540 of an SoC integratedcircuit that may be fabricated using one or more IP cores, in accordancewith at least one embodiment. In at least one embodiment, graphicsprocessor 4510 of FIG. 45A is a low power graphics processor core. In atleast one embodiment, graphics processor 4540 of FIG. 45B is a higherperformance graphics processor core. In at least one embodiment, each ofgraphics processors 4510, 4540 can be variants of graphics processor4010 of FIG. 40 .

In at least one embodiment, graphics processor 4510 includes a vertexprocessor 4505 and one or more fragment processor(s) 4515A-4515N (e.g.,4515A, 4515B, 4515C, 4515D, through 4515N−1, and 4515N). In at least oneembodiment, graphics processor 4510 can execute different shaderprograms via separate logic, such that vertex processor 4505 isoptimized to execute operations for vertex shader programs, while one ormore fragment processor(s) 4515A-4515N execute fragment (e.g., pixel)shading operations for fragment or pixel shader programs. In at leastone embodiment, vertex processor 4505 performs a vertex processing stageof a 3D graphics pipeline and generates primitives and vertex data. Inat least one embodiment, fragment processor(s) 4515A-4515N use primitiveand vertex data generated by vertex processor 4505 to produce aframebuffer that is displayed on a display device. In at least oneembodiment, fragment processor(s) 4515A-4515N are optimized to executefragment shader programs as provided for in an OpenGL API, which may beused to perform similar operations as a pixel shader program as providedfor in a Direct 3D API.

In at least one embodiment, graphics processor 4510 additionallyincludes one or more MMU(s) 4520A-4520B, cache(s) 4525A-4525B, andcircuit interconnect(s) 4530A-4530B. In at least one embodiment, one ormore MMU(s) 4520A-4520B provide for virtual to physical address mappingfor graphics processor 4510, including for vertex processor 4505 and/orfragment processor(s) 4515A-4515N, which may reference vertex orimage/texture data stored in memory, in addition to vertex orimage/texture data stored in one or more cache(s) 4525A-4525B. In atleast one embodiment, one or more MMU(s) 4520A-4520B may be synchronizedwith other MMUs within a system, including one or more MMUs associatedwith one or more application processor(s) 4005, image processors 4015,and/or video processors 4020 of FIG. 40 , such that each processor4005-4020 can participate in a shared or unified virtual memory system.In at least one embodiment, one or more circuit interconnect(s)4530A-4530B enable graphics processor 4510 to interface with other IPcores within an SoC, either via an internal bus of the SoC or via adirect connection.

In at least one embodiment, graphics processor 4540 includes one or moreMMU(s) 4520A-4520B, caches 4525A-4525B, and circuit interconnects4530A-4530B of graphics processor 4510 of FIG. 45A. In at least oneembodiment, graphics processor 4540 includes one or more shader core(s)4555A-4555N (e.g., 4555A, 4555B, 4555C, 4555D, 4555E, 4555F, through4555N−1, and 4555N), which provides for a unified shader corearchitecture in which a single core or type or core can execute alltypes of programmable shader code, including shader program code toimplement vertex shaders, fragment shaders, and/or compute shaders. Inat least one embodiment, a number of shader cores can vary. In at leastone embodiment, graphics processor 4540 includes an inter-core taskmanager 4545, which acts as a thread dispatcher to dispatch executionthreads to one or more shader cores 4555A-4555N and a tiling unit 4558to accelerate tiling operations for tile-based rendering, in whichrendering operations for a scene are subdivided in image space, forexample to exploit local spatial coherence within a scene or to optimizeuse of internal caches.

In at least one embodiment, at least one component shown or describedwith respect to FIG. 45A and FIG. 45B is used to implement techniquesand/or functions described in connection with FIGS. 1-35 . In at leastone embodiment, at least one of graphics processor 4510 or graphicsprocessor 4540 is used to perform an application programming interfaceto indicate two or more blocks of threads to be scheduled in parallel.In at least one embodiment, at least one of graphics processor 4510 orgraphics processor 4540 is used to perform an application programminginterface to determine which of two or more blocks of threads to bescheduled in parallel. In at least one embodiment, at least one ofgraphics processor 4510 or graphics processor 4540 is used to perform anapplication programming interface comprising one or more parameters tocause a scheduling policy of one or more blocks of one or more threadsto be performed. In at least one embodiment, at least one of graphicsprocessor 4510 or graphics processor 4540 is used to perform anapplication programming interface comprising one or more parameters toindicate a scheduling policy of one or more blocks of one or morethreads. In at least one embodiment, at least one of graphics processor4510 or graphics processor 4540 is used to perform an applicationprogramming interface to indicate a maximum number of blocks of threadscapable of being scheduled in parallel. In at least one embodiment, atleast one of graphics processor 4510 or graphics processor 4540 is usedto perform an application programming interface comprising one or moreparameters to indicate one or more attributes of one or more groups ofblocks of one or more threads. In at least one embodiment, at least oneof graphics processor 4510 or graphics processor 4540 is used to performan application programming interface to indicate a maximum number ofblocks of threads to be scheduled in parallel. In at least oneembodiment, at least one of graphics processor 4510 or graphicsprocessor 4540 is used to perform an application programming interfaceto cause a kernel to be generated to cause two or more blocks of two ormore threads to be scheduled in parallel. In at least one embodiment, atleast one of graphics processor 4510 or graphics processor 4540 is usedto perform an application programming interface comprising one or moreparameters to indicate one or more limitations of one or more attributesof one or more groups of blocks of one or more threads. In at least oneembodiment, at least one of graphics processor 4510 or graphicsprocessor 4540 is used to perform an application programming interfaceto indicate whether one or more threads within two or more blocks ofthreads have performed a barrier instruction. In at least oneembodiment, at least one of graphics processor 4510 or graphicsprocessor 4540 is used to perform an application programming interfaceto cause performance of one or more threads within a group of blocks ofthreads to stop at least until all threads within the group of blockshave performed a barrier instruction. In at least one embodiment, atleast one of graphics processor 4510 or graphics processor 4540 is usedto perform an application programming interface to indicate whether oneor more threads within two or more blocks of threads have performed abarrier instruction and to cause performance of one or more threadswithin the group of blocks of threads to stop at least until all threadswithin the group of blocks have performed the barrier instruction. In atleast one embodiment, at least one of graphics processor 4510 orgraphics processor 4540 is used to perform an application programminginterface to cause memory to be shared between two or more groups ofblocks of threads.

In at least one embodiment, at least one of graphics processor 4510 orgraphics processor 4540 is used to perform at least one aspect describedwith respect to example computer system 100, example diagram 200,example diagram 300, example diagram 400, example diagram 500, exampleprocess 600, example diagram 700, example application programminginterface 800, example application programming interface 900, examplediagram 1000, example diagram 1100, example application programminginterface 1200, example application programming interface 1300, examplecomputer system 1400, example application programming interface 1500,example diagram 1600, example application programming interface 1700,example computer system 1800, example application programming interface1900, example computer system 2000, example application programminginterface 2100, example diagram 2200, example diagram 2300, examplediagram 2400, example diagram 2500, example application programminginterface 2600, example diagram 2700, example diagram 2800, examplediagram 2900, example application programming interface 3000, exampleapplication programming interface 3100, example application programminginterface 3200, example diagram 3300, example application programminginterface 3400, example software stack 3500, and/or other systems,methods, or operations described herein.

FIG. 46A illustrates a graphics core 4600, in accordance with at leastone embodiment. In at least one embodiment, graphics core 4600 may beincluded within graphics processor 4010 of FIG. 40 . In at least oneembodiment, graphics core 4600 may be a unified shader core 4555A-4555Nas in FIG. 45B. In at least one embodiment, graphics core 4600 includesa shared instruction cache 4602, a texture unit 4618, and a cache/sharedmemory 4620 that are common to execution resources within graphics core4600. In at least one embodiment, graphics core 4600 can includemultiple slices 4601A-4601N or partition for each core, and a graphicsprocessor can include multiple instances of graphics core 4600. Slices4601A-4601N can include support logic including a local instructioncache 4604A-4604N, a thread scheduler 4606A-4606N, a thread dispatcher4608A-4608N, and a set of registers 4610A-4610N. In at least oneembodiment, slices 4601A-4601N can include a set of additional functionunits (“AFUs”) 4612A-4612N, floating-point units (“FPUs”) 4614A-4614N,integer arithmetic logic units (“ALUs”) 4616-4616N, addresscomputational units (“ACUs”) 4613A-4613N, double-precisionfloating-point units (“DPFPUs”) 4615A-4615N, and matrix processing units(“MPUs”) 4617A-4617N.

In at least one embodiment, FPUs 4614A-4614N can performsingle-precision (32-bit) and half-precision (16-bit) floating pointoperations, while DPFPUs 4615A-4615N perform double precision (64-bit)floating point operations. In at least one embodiment, ALUs 4616A-4616Ncan perform variable precision integer operations at 8-bit, 16-bit, and32-bit precision, and can be configured for mixed precision operations.In at least one embodiment, MPUs 4617A-4617N can also be configured formixed precision matrix operations, including half-precision floatingpoint and 8-bit integer operations. In at least one embodiment, MPUs4617-4617N can perform a variety of matrix operations to accelerate CUDAprograms, including enabling support for accelerated general matrix tomatrix multiplication (“GEMM”). In at least one embodiment, AFUs4612A-4612N can perform additional logic operations not supported byfloating-point or integer units, including trigonometric operations(e.g., Sine, Cosine, etc.).

In at least one embodiment, at least one component shown or describedwith respect to FIG. 46A is used to implement techniques and/orfunctions described in connection with FIGS. 1-35 . In at least oneembodiment, graphics core 4600 is used to perform an applicationprogramming interface to indicate two or more blocks of threads to bescheduled in parallel. In at least one embodiment, graphics core 4600 isused to perform an application programming interface to determine whichof two or more blocks of threads to be scheduled in parallel. In atleast one embodiment, graphics core 4600 is used to perform anapplication programming interface comprising one or more parameters tocause a scheduling policy of one or more blocks of one or more threadsto be performed. In at least one embodiment, graphics core 4600 is usedto perform an application programming interface comprising one or moreparameters to indicate a scheduling policy of one or more blocks of oneor more threads. In at least one embodiment, graphics core 4600 is usedto perform an application programming interface to indicate a maximumnumber of blocks of threads capable of being scheduled in parallel. Inat least one embodiment, graphics core 4600 is used to perform anapplication programming interface comprising one or more parameters toindicate one or more attributes of one or more groups of blocks of oneor more threads. In at least one embodiment, graphics core 4600 is usedto perform an application programming interface to indicate a maximumnumber of blocks of threads to be scheduled in parallel. In at least oneembodiment, graphics core 4600 is used to perform an applicationprogramming interface to cause a kernel to be generated to cause two ormore blocks of two or more threads to be scheduled in parallel. In atleast one embodiment, graphics core 4600 is used to perform anapplication programming interface comprising one or more parameters toindicate one or more limitations of one or more attributes of one ormore groups of blocks of one or more threads. In at least oneembodiment, graphics core 4600 is used to perform an applicationprogramming interface to indicate whether one or more threads within twoor more blocks of threads have performed a barrier instruction. In atleast one embodiment, graphics core 4600 is used to perform anapplication programming interface to cause performance of one or morethreads within a group of blocks of threads to stop at least until allthreads within the group of blocks have performed a barrier instruction.In at least one embodiment, graphics core 4600 is used to perform anapplication programming interface to indicate whether one or morethreads within two or more blocks of threads have performed a barrierinstruction and to cause performance of one or more threads within thegroup of blocks of threads to stop at least until all threads within thegroup of blocks have performed the barrier instruction. In at least oneembodiment, graphics core 4600 is used to perform an applicationprogramming interface to cause memory to be shared between two or moregroups of blocks of threads.

In at least one embodiment, graphics core 4600 is used to perform atleast one aspect described with respect to example computer system 100,example diagram 200, example diagram 300, example diagram 400, examplediagram 500, example process 600, example diagram 700, exampleapplication programming interface 800, example application programminginterface 900, example diagram 1000, example diagram 1100, exampleapplication programming interface 1200, example application programminginterface 1300, example computer system 1400, example applicationprogramming interface 1500, example diagram 1600, example applicationprogramming interface 1700, example computer system 1800, exampleapplication programming interface 1900, example computer system 2000,example application programming interface 2100, example diagram 2200,example diagram 2300, example diagram 2400, example diagram 2500,example application programming interface 2600, example diagram 2700,example diagram 2800, example diagram 2900, example applicationprogramming interface 3000, example application programming interface3100, example application programming interface 3200, example diagram3300, example application programming interface 3400, example softwarestack 3500, and/or other systems, methods, or operations describedherein.

FIG. 46B illustrates a general-purpose graphics processing unit(“GPGPU”) 4630, in accordance with at least one embodiment. In at leastone embodiment, GPGPU 4630 is highly-parallel and suitable fordeployment on a multi-chip module. In at least one embodiment, GPGPU4630 can be configured to enable highly-parallel compute operations tobe performed by an array of GPUs. In at least one embodiment, GPGPU 4630can be linked directly to other instances of GPGPU 4630 to create amulti-GPU cluster to improve execution time for CUDA programs. In atleast one embodiment, GPGPU 4630 includes a host interface 4632 toenable a connection with a host processor. In at least one embodiment,host interface 4632 is a PCIe interface. In at least one embodiment,host interface 4632 can be a vendor specific communications interface orcommunications fabric. In at least one embodiment, GPGPU 4630 receivescommands from a host processor and uses a global scheduler 4634 todistribute execution threads associated with those commands to a set ofcompute clusters 4636A-4636H. In at least one embodiment, computeclusters 4636A-4636H share a cache memory 4638. In at least oneembodiment, cache memory 4638 can serve as a higher-level cache forcache memories within compute clusters 4636A-4636H.

In at least one embodiment, GPGPU 4630 includes memory 4644A-4644Bcoupled with compute clusters 4636A-4636H via a set of memorycontrollers 4642A-4642B. In at least one embodiment, memory 4644A-4644Bcan include various types of memory devices including DRAM or graphicsrandom access memory, such as synchronous graphics random access memory(“SGRAM”), including graphics double data rate (“GDDR”) memory.

In at least one embodiment, compute clusters 4636A-4636H each include aset of graphics cores, such as graphics core 4600 of FIG. 46A, which caninclude multiple types of integer and floating point logic units thatcan perform computational operations at a range of precisions includingsuited for computations associated with CUDA programs. For example, inat least one embodiment, at least a subset of floating point units ineach of compute clusters 4636A-4636H can be configured to perform 16-bitor 32-bit floating point operations, while a different subset offloating point units can be configured to perform 64-bit floating pointoperations.

In at least one embodiment, multiple instances of GPGPU 4630 can beconfigured to operate as a compute cluster. Compute clusters 4636A-4636Hmay implement any technically feasible communication techniques forsynchronization and data exchange. In at least one embodiment, multipleinstances of GPGPU 4630 communicate over host interface 4632. In atleast one embodiment, GPGPU 4630 includes an I/O hub 4639 that couplesGPGPU 4630 with a GPU link 4640 that enables a direct connection toother instances of GPGPU 4630. In at least one embodiment, GPU link 4640is coupled to a dedicated GPU-to-GPU bridge that enables communicationand synchronization between multiple instances of GPGPU 4630. In atleast one embodiment GPU link 4640 couples with a high speedinterconnect to transmit and receive data to other GPGPUs 4630 orparallel processors. In at least one embodiment, multiple instances ofGPGPU 4630 are located in separate data processing systems andcommunicate via a network device that is accessible via host interface4632. In at least one embodiment GPU link 4640 can be configured toenable a connection to a host processor in addition to or as analternative to host interface 4632. In at least one embodiment, GPGPU4630 can be configured to execute a CUDA program.

In at least one embodiment, at least one component shown or describedwith respect to FIG. 46B is used to implement techniques and/orfunctions described in connection with FIGS. 1-35 . In at least oneembodiment, GPGPU 4630 is used to perform an application programminginterface to indicate two or more blocks of threads to be scheduled inparallel. In at least one embodiment, GPGPU 4630 is used to perform anapplication programming interface to determine which of two or moreblocks of threads to be scheduled in parallel. In at least oneembodiment, GPGPU 4630 is used to perform an application programminginterface comprising one or more parameters to cause a scheduling policyof one or more blocks of one or more threads to be performed. In atleast one embodiment, GPGPU 4630 is used to perform an applicationprogramming interface comprising one or more parameters to indicate ascheduling policy of one or more blocks of one or more threads. In atleast one embodiment, GPGPU 4630 is used to perform an applicationprogramming interface to indicate a maximum number of blocks of threadscapable of being scheduled in parallel. In at least one embodiment,GPGPU 4630 is used to perform an application programming interfacecomprising one or more parameters to indicate one or more attributes ofone or more groups of blocks of one or more threads. In at least oneembodiment, GPGPU 4630 is used to perform an application programminginterface to indicate a maximum number of blocks of threads to bescheduled in parallel. In at least one embodiment, GPGPU 4630 is used toperform an application programming interface to cause a kernel to begenerated to cause two or more blocks of two or more threads to bescheduled in parallel. In at least one embodiment, GPGPU 4630 is used toperform an application programming interface comprising one or moreparameters to indicate one or more limitations of one or more attributesof one or more groups of blocks of one or more threads. In at least oneembodiment, GPGPU 4630 is used to perform an application programminginterface to indicate whether one or more threads within two or moreblocks of threads have performed a barrier instruction. In at least oneembodiment, GPGPU 4630 is used to perform an application programminginterface to cause performance of one or more threads within a group ofblocks of threads to stop at least until all threads within the group ofblocks have performed a barrier instruction. In at least one embodiment,GPGPU 4630 is used to perform an application programming interface toindicate whether one or more threads within two or more blocks ofthreads have performed a barrier instruction and to cause performance ofone or more threads within the group of blocks of threads to stop atleast until all threads within the group of blocks have performed thebarrier instruction. In at least one embodiment, GPGPU 4630 is used toperform an application programming interface to cause memory to beshared between two or more groups of blocks of threads.

In at least one embodiment, GPGPU 4630 is used to perform at least oneaspect described with respect to example computer system 100, examplediagram 200, example diagram 300, example diagram 400, example diagram500, example process 600, example diagram 700, example applicationprogramming interface 800, example application programming interface900, example diagram 1000, example diagram 1100, example applicationprogramming interface 1200, example application programming interface1300, example computer system 1400, example application programminginterface 1500, example diagram 1600, example application programminginterface 1700, example computer system 1800, example applicationprogramming interface 1900, example computer system 2000, exampleapplication programming interface 2100, example diagram 2200, examplediagram 2300, example diagram 2400, example diagram 2500, exampleapplication programming interface 2600, example diagram 2700, examplediagram 2800, example diagram 2900, example application programminginterface 3000, example application programming interface 3100, exampleapplication programming interface 3200, example diagram 3300, exampleapplication programming interface 3400, example software stack 3500,and/or other systems, methods, or operations described herein.

FIG. 47A illustrates a parallel processor 4700, in accordance with atleast one embodiment. In at least one embodiment, various components ofparallel processor 4700 may be implemented using one or more integratedcircuit devices, such as programmable processors, application specificintegrated circuits (“ASICs”), or FPGAs.

In at least one embodiment, parallel processor 4700 includes a parallelprocessing unit 4702. In at least one embodiment, parallel processingunit 4702 includes an I/O unit 4704 that enables communication withother devices, including other instances of parallel processing unit4702. In at least one embodiment, I/O unit 4704 may be directlyconnected to other devices. In at least one embodiment, I/O unit 4704connects with other devices via use of a hub or switch interface, suchas memory hub 4705. In at least one embodiment, connections betweenmemory hub 4705 and I/O unit 4704 form a communication link. In at leastone embodiment, I/O unit 4704 connects with a host interface 4706 and amemory crossbar 4716, where host interface 4706 receives commandsdirected to performing processing operations and memory crossbar 4716receives commands directed to performing memory operations.

In at least one embodiment, when host interface 4706 receives a commandbuffer via I/O unit 4704, host interface 4706 can direct work operationsto perform those commands to a front end 4708. In at least oneembodiment, front end 4708 couples with a scheduler 4710, which isconfigured to distribute commands or other work items to a processingarray 4712. In at least one embodiment, scheduler 4710 ensures thatprocessing array 4712 is properly configured and in a valid state beforetasks are distributed to processing array 4712. In at least oneembodiment, scheduler 4710 is implemented via firmware logic executingon a microcontroller. In at least one embodiment, microcontrollerimplemented scheduler 4710 is configurable to perform complex schedulingand work distribution operations at coarse and fine granularity,enabling rapid preemption and context switching of threads executing onprocessing array 4712. In at least one embodiment, host software canprove workloads for scheduling on processing array 4712 via one ofmultiple graphics processing doorbells. In at least one embodiment,workloads can then be automatically distributed across processing array4712 by scheduler 4710 logic within a microcontroller includingscheduler 4710.

In at least one embodiment, processing array 4712 can include up to “N”clusters (e.g., cluster 4714A, cluster 4714B, through cluster 4714N). Inat least one embodiment, each cluster 4714A-4714N of processing array4712 can execute a large number of concurrent threads. In at least oneembodiment, scheduler 4710 can allocate work to clusters 4714A-4714N ofprocessing array 4712 using various scheduling and/or work distributionalgorithms, which may vary depending on the workload arising for eachtype of program or computation. In at least one embodiment, schedulingcan be handled dynamically by scheduler 4710, or can be assisted in partby compiler logic during compilation of program logic configured forexecution by processing array 4712. In at least one embodiment,different clusters 4714A-4714N of processing array 4712 can be allocatedfor processing different types of programs or for performing differenttypes of computations.

In at least one embodiment, processing array 4712 can be configured toperform various types of parallel processing operations. In at least oneembodiment, processing array 4712 is configured to performgeneral-purpose parallel compute operations. For example, in at leastone embodiment, processing array 4712 can include logic to executeprocessing tasks including filtering of video and/or audio data,performing modeling operations, including physics operations, andperforming data transformations.

In at least one embodiment, processing array 4712 is configured toperform parallel graphics processing operations. In at least oneembodiment, processing array 4712 can include additional logic tosupport execution of such graphics processing operations, including, butnot limited to texture sampling logic to perform texture operations, aswell as tessellation logic and other vertex processing logic. In atleast one embodiment, processing array 4712 can be configured to executegraphics processing related shader programs such as, but not limited tovertex shaders, tessellation shaders, geometry shaders, and pixelshaders. In at least one embodiment, parallel processing unit 4702 cantransfer data from system memory via I/O unit 4704 for processing. In atleast one embodiment, during processing, transferred data can be storedto on-chip memory (e.g., a parallel processor memory 4722) duringprocessing, then written back to system memory.

In at least one embodiment, when parallel processing unit 4702 is usedto perform graphics processing, scheduler 4710 can be configured todivide a processing workload into approximately equal sized tasks, tobetter enable distribution of graphics processing operations to multipleclusters 4714A-4714N of processing array 4712. In at least oneembodiment, portions of processing array 4712 can be configured toperform different types of processing. For example, in at least oneembodiment, a first portion may be configured to perform vertex shadingand topology generation, a second portion may be configured to performtessellation and geometry shading, and a third portion may be configuredto perform pixel shading or other screen space operations, to produce arendered image for display. In at least one embodiment, intermediatedata produced by one or more of clusters 4714A-4714N may be stored inbuffers to allow intermediate data to be transmitted between clusters4714A-4714N for further processing.

In at least one embodiment, processing array 4712 can receive processingtasks to be executed via scheduler 4710, which receives commandsdefining processing tasks from front end 4708. In at least oneembodiment, processing tasks can include indices of data to beprocessed, e.g., surface (patch) data, primitive data, vertex data,and/or pixel data, as well as state parameters and commands defining howdata is to be processed (e.g., what program is to be executed). In atleast one embodiment, scheduler 4710 may be configured to fetch indicescorresponding to tasks or may receive indices from front end 4708. In atleast one embodiment, front end 4708 can be configured to ensureprocessing array 4712 is configured to a valid state before a workloadspecified by incoming command buffers (e.g., batch-buffers, pushbuffers, etc.) is initiated.

In at least one embodiment, each of one or more instances of parallelprocessing unit 4702 can couple with parallel processor memory 4722. Inat least one embodiment, parallel processor memory 4722 can be accessedvia memory crossbar 4716, which can receive memory requests fromprocessing array 4712 as well as I/O unit 4704. In at least oneembodiment, memory crossbar 4716 can access parallel processor memory4722 via a memory interface 4718. In at least one embodiment, memoryinterface 4718 can include multiple partition units (e.g., a partitionunit 4720A, partition unit 4720B, through partition unit 4720N) that caneach couple to a portion (e.g., memory unit) of parallel processormemory 4722. In at least one embodiment, a number of partition units4720A-4720N is configured to be equal to a number of memory units, suchthat a first partition unit 4720A has a corresponding first memory unit4724A, a second partition unit 4720B has a corresponding memory unit4724B, and an Nth partition unit 4720N has a corresponding Nth memoryunit 4724N. In at least one embodiment, a number of partition units4720A-4720N may not be equal to a number of memory devices.

In at least one embodiment, memory units 4724A-4724N can include varioustypes of memory devices, including DRAM or graphics random accessmemory, such as SGRAM, including GDDR memory. In at least oneembodiment, memory units 4724A-4724N may also include 3D stacked memory,including but not limited to high bandwidth memory (“HBM”). In at leastone embodiment, render targets, such as frame buffers or texture mapsmay be stored across memory units 4724A-4724N, allowing partition units4720A-4720N to write portions of each render target in parallel toefficiently use available bandwidth of parallel processor memory 4722.In at least one embodiment, a local instance of parallel processormemory 4722 may be excluded in favor of a unified memory design thatutilizes system memory in conjunction with local cache memory.

In at least one embodiment, any one of clusters 4714A-4714N ofprocessing array 4712 can process data that will be written to any ofmemory units 4724A-4724N within parallel processor memory 4722. In atleast one embodiment, memory crossbar 4716 can be configured to transferan output of each cluster 4714A-4714N to any partition unit 4720A-4720Nor to another cluster 4714A-4714N, which can perform additionalprocessing operations on an output. In at least one embodiment, eachcluster 4714A-4714N can communicate with memory interface 4718 throughmemory crossbar 4716 to read from or write to various external memorydevices. In at least one embodiment, memory crossbar 4716 has aconnection to memory interface 4718 to communicate with I/O unit 4704,as well as a connection to a local instance of parallel processor memory4722, enabling processing units within different clusters 4714A-4714N tocommunicate with system memory or other memory that is not local toparallel processing unit 4702. In at least one embodiment, memorycrossbar 4716 can use virtual channels to separate traffic streamsbetween clusters 4714A-4714N and partition units 4720A-4720N.

In at least one embodiment, multiple instances of parallel processingunit 4702 can be provided on a single add-in card, or multiple add-incards can be interconnected. In at least one embodiment, differentinstances of parallel processing unit 4702 can be configured tointeroperate even if different instances have different numbers ofprocessing cores, different amounts of local parallel processor memory,and/or other configuration differences. For example, in at least oneembodiment, some instances of parallel processing unit 4702 can includehigher precision floating point units relative to other instances. In atleast one embodiment, systems incorporating one or more instances ofparallel processing unit 4702 or parallel processor 4700 can beimplemented in a variety of configurations and form factors, includingbut not limited to desktop, laptop, or handheld personal computers,servers, workstations, game consoles, and/or embedded systems.

In at least one embodiment, at least one component shown or describedwith respect to FIG. 47A is used to implement techniques and/orfunctions described in connection with FIGS. 1-35 . In at least oneembodiment, parallel processor 4700 is used to perform an applicationprogramming interface to indicate two or more blocks of threads to bescheduled in parallel. In at least one embodiment, parallel processor4700 is used to perform an application programming interface todetermine which of two or more blocks of threads to be scheduled inparallel. In at least one embodiment, parallel processor 4700 is used toperform an application programming interface comprising one or moreparameters to cause a scheduling policy of one or more blocks of one ormore threads to be performed. In at least one embodiment, parallelprocessor 4700 is used to perform an application programming interfacecomprising one or more parameters to indicate a scheduling policy of oneor more blocks of one or more threads. In at least one embodiment,parallel processor 4700 is used to perform an application programminginterface to indicate a maximum number of blocks of threads capable ofbeing scheduled in parallel. In at least one embodiment, parallelprocessor 4700 is used to perform an application programming interfacecomprising one or more parameters to indicate one or more attributes ofone or more groups of blocks of one or more threads. In at least oneembodiment, parallel processor 4700 is used to perform an applicationprogramming interface to indicate a maximum number of blocks of threadsto be scheduled in parallel. In at least one embodiment, parallelprocessor 4700 is used to perform an application programming interfaceto cause a kernel to be generated to cause two or more blocks of two ormore threads to be scheduled in parallel. In at least one embodiment,parallel processor 4700 is used to perform an application programminginterface comprising one or more parameters to indicate one or morelimitations of one or more attributes of one or more groups of blocks ofone or more threads. In at least one embodiment, parallel processor 4700is used to perform an application programming interface to indicatewhether one or more threads within two or more blocks of threads haveperformed a barrier instruction. In at least one embodiment, parallelprocessor 4700 is used to perform an application programming interfaceto cause performance of one or more threads within a group of blocks ofthreads to stop at least until all threads within the group of blockshave performed a barrier instruction. In at least one embodiment,parallel processor 4700 is used to perform an application programminginterface to indicate whether one or more threads within two or moreblocks of threads have performed a barrier instruction and to causeperformance of one or more threads within the group of blocks of threadsto stop at least until all threads within the group of blocks haveperformed the barrier instruction. In at least one embodiment, parallelprocessor 4700 is used to perform an application programming interfaceto cause memory to be shared between two or more groups of blocks ofthreads.

In at least one embodiment, parallel processor 4700 is used to performat least one aspect described with respect to example computer system100, example diagram 200, example diagram 300, example diagram 400,example diagram 500, example process 600, example diagram 700, exampleapplication programming interface 800, example application programminginterface 900, example diagram 1000, example diagram 1100, exampleapplication programming interface 1200, example application programminginterface 1300, example computer system 1400, example applicationprogramming interface 1500, example diagram 1600, example applicationprogramming interface 1700, example computer system 1800, exampleapplication programming interface 1900, example computer system 2000,example application programming interface 2100, example diagram 2200,example diagram 2300, example diagram 2400, example diagram 2500,example application programming interface 2600, example diagram 2700,example diagram 2800, example diagram 2900, example applicationprogramming interface 3000, example application programming interface3100, example application programming interface 3200, example diagram3300, example application programming interface 3400, example softwarestack 3500, and/or other systems, methods, or operations describedherein.

FIG. 47B illustrates a processing cluster 4794, in accordance with atleast one embodiment. In at least one embodiment, processing cluster4794 is included within a parallel processing unit. In at least oneembodiment, processing cluster 4794 is one of processing clusters4714A-4714N of FIG. 47 . In at least one embodiment, processing cluster4794 can be configured to execute many threads in parallel, where theterm “thread” refers to an instance of a particular program executing ona particular set of input data. In at least one embodiment, singleinstruction, multiple data (“SIMD”) instruction issue techniques areused to support parallel execution of a large number of threads withoutproviding multiple independent instruction units. In at least oneembodiment, single instruction, multiple thread (“SIMT”) techniques areused to support parallel execution of a large number of generallysynchronized threads, using a common instruction unit configured toissue instructions to a set of processing engines within each processingcluster 4794.

In at least one embodiment, operation of processing cluster 4794 can becontrolled via a pipeline manager 4732 that distributes processing tasksto SIMT parallel processors. In at least one embodiment, pipelinemanager 4732 receives instructions from scheduler 4710 of FIG. 47 andmanages execution of those instructions via a graphics multiprocessor4734 and/or a texture unit 4736. In at least one embodiment, graphicsmultiprocessor 4734 is an exemplary instance of a SIMT parallelprocessor. However, in at least one embodiment, various types of SIMTparallel processors of differing architectures may be included withinprocessing cluster 4794. In at least one embodiment, one or moreinstances of graphics multiprocessor 4734 can be included withinprocessing cluster 4794. In at least one embodiment, graphicsmultiprocessor 4734 can process data and a data crossbar 4740 can beused to distribute processed data to one of multiple possibledestinations, including other shader units. In at least one embodiment,pipeline manager 4732 can facilitate distribution of processed data byspecifying destinations for processed data to be distributed via datacrossbar 4740.

In at least one embodiment, each graphics multiprocessor 4734 withinprocessing cluster 4794 can include an identical set of functionalexecution logic (e.g., arithmetic logic units, load/store units(“LSUs”), etc.). In at least one embodiment, functional execution logiccan be configured in a pipelined manner in which new instructions can beissued before previous instructions are complete. In at least oneembodiment, functional execution logic supports a variety of operationsincluding integer and floating point arithmetic, comparison operations,Boolean operations, bit-shifting, and computation of various algebraicfunctions. In at least one embodiment, same functional-unit hardware canbe leveraged to perform different operations and any combination offunctional units may be present.

In at least one embodiment, instructions transmitted to processingcluster 4794 constitute a thread. In at least one embodiment, a set ofthreads executing across a set of parallel processing engines is athread group. In at least one embodiment, a thread group executes aprogram on different input data. In at least one embodiment, each threadwithin a thread group can be assigned to a different processing enginewithin graphics multiprocessor 4734. In at least one embodiment, athread group may include fewer threads than a number of processingengines within graphics multiprocessor 4734. In at least one embodiment,when a thread group includes fewer threads than a number of processingengines, one or more of the processing engines may be idle during cyclesin which that thread group is being processed. In at least oneembodiment, a thread group may also include more threads than a numberof processing engines within graphics multiprocessor 4734. In at leastone embodiment, when a thread group includes more threads than thenumber of processing engines within graphics multiprocessor 4734,processing can be performed over consecutive clock cycles. In at leastone embodiment, multiple thread groups can be executed concurrently ongraphics multiprocessor 4734.

In at least one embodiment, graphics multiprocessor 4734 includes aninternal cache memory to perform load and store operations. In at leastone embodiment, graphics multiprocessor 4734 can forego an internalcache and use a cache memory (e.g., L1 cache 4748) within processingcluster 4794. In at least one embodiment, each graphics multiprocessor4734 also has access to Level 2 (“L2”) caches within partition units(e.g., partition units 4720A-4720N of FIG. 47A) that are shared amongall processing clusters 4794 and may be used to transfer data betweenthreads. In at least one embodiment, graphics multiprocessor 4734 mayalso access off-chip global memory, which can include one or more oflocal parallel processor memory and/or system memory. In at least oneembodiment, any memory external to parallel processing unit 4702 may beused as global memory. In at least one embodiment, processing cluster4794 includes multiple instances of graphics multiprocessor 4734 thatcan share common instructions and data, which may be stored in L1 cache4748.

In at least one embodiment, each processing cluster 4794 may include anMMU 4745 that is configured to map virtual addresses into physicaladdresses. In at least one embodiment, one or more instances of MMU 4745may reside within memory interface 4718 of FIG. 47 . In at least oneembodiment, MMU 4745 includes a set of page table entries (“PTEs”) usedto map a virtual address to a physical address of a tile and optionallya cache line index. In at least one embodiment, MMU 4745 may includeaddress translation lookaside buffers (“TLBs”) or caches that may residewithin graphics multiprocessor 4734 or L1 cache 4748 or processingcluster 4794. In at least one embodiment, a physical address isprocessed to distribute surface data access locality to allow efficientrequest interleaving among partition units. In at least one embodiment,a cache line index may be used to determine whether a request for acache line is a hit or miss.

In at least one embodiment, processing cluster 4794 may be configuredsuch that each graphics multiprocessor 4734 is coupled to a texture unit4736 for performing texture mapping operations, e.g., determiningtexture sample positions, reading texture data, and filtering texturedata. In at least one embodiment, texture data is read from an internaltexture L1 cache (not shown) or from an L1 cache within graphicsmultiprocessor 4734 and is fetched from an L2 cache, local parallelprocessor memory, or system memory, as needed. In at least oneembodiment, each graphics multiprocessor 4734 outputs a processed taskto data crossbar 4740 to provide the processed task to anotherprocessing cluster 4794 for further processing or to store the processedtask in an L2 cache, a local parallel processor memory, or a systemmemory via memory crossbar 4716. In at least one embodiment, apre-raster operations unit (“preROP”) 4742 is configured to receive datafrom graphics multiprocessor 4734, direct data to ROP units, which maybe located with partition units as described herein (e.g., partitionunits 4720A-4720N of FIG. 47 ). In at least one embodiment, PreROP 4742can perform optimizations for color blending, organize pixel color data,and perform address translations.

In at least one embodiment, at least one component shown or describedwith respect to FIG. 47B is used to implement techniques and/orfunctions described in connection with FIGS. 1-35 . In at least oneembodiment, graphics multiprocessor 4734 is used to perform anapplication programming interface to indicate two or more blocks ofthreads to be scheduled in parallel. In at least one embodiment,graphics multiprocessor 4734 is used to perform an applicationprogramming interface to determine which of two or more blocks ofthreads to be scheduled in parallel. In at least one embodiment,graphics multiprocessor 4734 is used to perform an applicationprogramming interface comprising one or more parameters to cause ascheduling policy of one or more blocks of one or more threads to beperformed. In at least one embodiment, graphics multiprocessor 4734 isused to perform an application programming interface comprising one ormore parameters to indicate a scheduling policy of one or more blocks ofone or more threads. In at least one embodiment, graphics multiprocessor4734 is used to perform an application programming interface to indicatea maximum number of blocks of threads capable of being scheduled inparallel. In at least one embodiment, graphics multiprocessor 4734 isused to perform an application programming interface comprising one ormore parameters to indicate one or more attributes of one or more groupsof blocks of one or more threads. In at least one embodiment, graphicsmultiprocessor 4734 is used to perform an application programminginterface to indicate a maximum number of blocks of threads to bescheduled in parallel. In at least one embodiment, graphicsmultiprocessor 4734 is used to perform an application programminginterface to cause a kernel to be generated to cause two or more blocksof two or more threads to be scheduled in parallel. In at least oneembodiment, graphics multiprocessor 4734 is used to perform anapplication programming interface comprising one or more parameters toindicate one or more limitations of one or more attributes of one ormore groups of blocks of one or more threads. In at least oneembodiment, graphics multiprocessor 4734 is used to perform anapplication programming interface to indicate whether one or morethreads within two or more blocks of threads have performed a barrierinstruction. In at least one embodiment, graphics multiprocessor 4734 isused to perform an application programming interface to causeperformance of one or more threads within a group of blocks of threadsto stop at least until all threads within the group of blocks haveperformed a barrier instruction. In at least one embodiment, graphicsmultiprocessor 4734 is used to perform an application programminginterface to indicate whether one or more threads within two or moreblocks of threads have performed a barrier instruction and to causeperformance of one or more threads within the group of blocks of threadsto stop at least until all threads within the group of blocks haveperformed the barrier instruction. In at least one embodiment, graphicsmultiprocessor 4734 is used to perform an application programminginterface to cause memory to be shared between two or more groups ofblocks of threads.

In at least one embodiment, graphics multiprocessor 4734 is used toperform at least one aspect described with respect to example computersystem 100, example diagram 200, example diagram 300, example diagram400, example diagram 500, example process 600, example diagram 700,example application programming interface 800, example applicationprogramming interface 900, example diagram 1000, example diagram 1100,example application programming interface 1200, example applicationprogramming interface 1300, example computer system 1400, exampleapplication programming interface 1500, example diagram 1600, exampleapplication programming interface 1700, example computer system 1800,example application programming interface 1900, example computer system2000, example application programming interface 2100, example diagram2200, example diagram 2300, example diagram 2400, example diagram 2500,example application programming interface 2600, example diagram 2700,example diagram 2800, example diagram 2900, example applicationprogramming interface 3000, example application programming interface3100, example application programming interface 3200, example diagram3300, example application programming interface 3400, example softwarestack 3500, and/or other systems, methods, or operations describedherein.

FIG. 47C illustrates a graphics multiprocessor 4796, in accordance withat least one embodiment. In at least one embodiment, graphicsmultiprocessor 4796 is graphics multiprocessor 4734 of FIG. 47B. In atleast one embodiment, graphics multiprocessor 4796 couples with pipelinemanager 4732 of processing cluster 4794. In at least one embodiment,graphics multiprocessor 4796 has an execution pipeline including but notlimited to an instruction cache 4752, an instruction unit 4754, anaddress mapping unit 4756, a register file 4758, one or more GPGPU cores4762, and one or more LSUs 4766. GPGPU cores 4762 and LSUs 4766 arecoupled with cache memory 4772 and shared memory 4770 via a memory andcache interconnect 4768.

In at least one embodiment, instruction cache 4752 receives a stream ofinstructions to execute from pipeline manager 4732. In at least oneembodiment, instructions are cached in instruction cache 4752 anddispatched for execution by instruction unit 4754. In at least oneembodiment, instruction unit 4754 can dispatch instructions as threadgroups (e.g., warps), with each thread of a thread group assigned to adifferent execution unit within GPGPU core 4762. In at least oneembodiment, an instruction can access any of a local, shared, or globaladdress space by specifying an address within a unified address space.In at least one embodiment, address mapping unit 4756 can be used totranslate addresses in a unified address space into a distinct memoryaddress that can be accessed by LSUs 4766.

In at least one embodiment, register file 4758 provides a set ofregisters for functional units of graphics multiprocessor 4796. In atleast one embodiment, register file 4758 provides temporary storage foroperands connected to data paths of functional units (e.g., GPGPU cores4762, LSUs 4766) of graphics multiprocessor 4796. In at least oneembodiment, register file 4758 is divided between each of functionalunits such that each functional unit is allocated a dedicated portion ofregister file 4758. In at least one embodiment, register file 4758 isdivided between different thread groups being executed by graphicsmultiprocessor 4796.

In at least one embodiment, GPGPU cores 4762 can each include FPUsand/or integer ALUs that are used to execute instructions of graphicsmultiprocessor 4796. GPGPU cores 4762 can be similar in architecture orcan differ in architecture. In at least one embodiment, a first portionof GPGPU cores 4762 include a single precision FPU and an integer ALUwhile a second portion of GPGPU cores 4762 include a double precisionFPU. In at least one embodiment, FPUs can implement IEEE 754-2008standard for floating point arithmetic or enable variable precisionfloating point arithmetic. In at least one embodiment, graphicsmultiprocessor 4796 can additionally include one or more fixed functionor special function units to perform specific functions such as copyrectangle or pixel blending operations. In at least one embodiment oneor more of GPGPU cores 4762 can also include fixed or special functionlogic.

In at least one embodiment, GPGPU cores 4762 include SIMD logic capableof performing a single instruction on multiple sets of data. In at leastone embodiment GPGPU cores 4762 can physically execute SIMD4, SIMD8, andSIMD16 instructions and logically execute SIMD1, SIMD2, and SIMD32instructions. In at least one embodiment, SIMD instructions for GPGPUcores 4762 can be generated at compile time by a shader compiler orautomatically generated when executing programs written and compiled forsingle program multiple data (“SPMD”) or SIMT architectures. In at leastone embodiment, multiple threads of a program configured for an SIMTexecution model can executed via a single SIMD instruction. For example,in at least one embodiment, eight SIMT threads that perform the same orsimilar operations can be executed in parallel via a single SIMD8 logicunit.

In at least one embodiment, memory and cache interconnect 4768 is aninterconnect network that connects each functional unit of graphicsmultiprocessor 4796 to register file 4758 and to shared memory 4770. Inat least one embodiment, memory and cache interconnect 4768 is acrossbar interconnect that allows LSU 4766 to implement load and storeoperations between shared memory 4770 and register file 4758. In atleast one embodiment, register file 4758 can operate at a same frequencyas GPGPU cores 4762, thus data transfer between GPGPU cores 4762 andregister file 4758 is very low latency. In at least one embodiment,shared memory 4770 can be used to enable communication between threadsthat execute on functional units within graphics multiprocessor 4796. Inat least one embodiment, cache memory 4772 can be used as a data cachefor example, to cache texture data communicated between functional unitsand texture unit 4736. In at least one embodiment, shared memory 4770can also be used as a program managed cached. In at least oneembodiment, threads executing on GPGPU cores 4762 can programmaticallystore data within shared memory in addition to automatically cached datathat is stored within cache memory 4772.

In at least one embodiment, a parallel processor or GPGPU as describedherein is communicatively coupled to host/processor cores to accelerategraphics operations, machine-learning operations, pattern analysisoperations, and various general purpose GPU (GPGPU) functions. In atleast one embodiment, a GPU may be communicatively coupled to hostprocessor/cores over a bus or other interconnect (e.g., a high speedinterconnect such as PCIe or NVLink). In at least one embodiment, a GPUmay be integrated on the same package or chip as cores andcommunicatively coupled to cores over a processor bus/interconnect thatis internal to a package or a chip. In at least one embodiment,regardless of the manner in which a GPU is connected, processor coresmay allocate work to the GPU in the form of sequences ofcommands/instructions contained in a WD. In at least one embodiment, theGPU then uses dedicated circuitry/logic for efficiently processing thesecommands/instructions.

In at least one embodiment, at least one component shown or describedwith respect to FIG. 47C is used to implement techniques and/orfunctions described in connection with FIGS. 1-35 . In at least oneembodiment, graphics multiprocessor 4796 is used to perform anapplication programming interface to indicate two or more blocks ofthreads to be scheduled in parallel. In at least one embodiment,graphics multiprocessor 4796 is used to perform an applicationprogramming interface to determine which of two or more blocks ofthreads to be scheduled in parallel. In at least one embodiment,graphics multiprocessor 4796 is used to perform an applicationprogramming interface comprising one or more parameters to cause ascheduling policy of one or more blocks of one or more threads to beperformed. In at least one embodiment, graphics multiprocessor 4796 isused to perform an application programming interface comprising one ormore parameters to indicate a scheduling policy of one or more blocks ofone or more threads. In at least one embodiment, graphics multiprocessor4796 is used to perform an application programming interface to indicatea maximum number of blocks of threads capable of being scheduled inparallel. In at least one embodiment, graphics multiprocessor 4796 isused to perform an application programming interface comprising one ormore parameters to indicate one or more attributes of one or more groupsof blocks of one or more threads. In at least one embodiment, graphicsmultiprocessor 4796 is used to perform an application programminginterface to indicate a maximum number of blocks of threads to bescheduled in parallel. In at least one embodiment, graphicsmultiprocessor 4796 is used to perform an application programminginterface to cause a kernel to be generated to cause two or more blocksof two or more threads to be scheduled in parallel. In at least oneembodiment, graphics multiprocessor 4796 is used to perform anapplication programming interface comprising one or more parameters toindicate one or more limitations of one or more attributes of one ormore groups of blocks of one or more threads. In at least oneembodiment, graphics multiprocessor 4796 is used to perform anapplication programming interface to indicate whether one or morethreads within two or more blocks of threads have performed a barrierinstruction. In at least one embodiment, graphics multiprocessor 4796 isused to perform an application programming interface to causeperformance of one or more threads within a group of blocks of threadsto stop at least until all threads within the group of blocks haveperformed a barrier instruction. In at least one embodiment, graphicsmultiprocessor 4796 is used to perform an application programminginterface to indicate whether one or more threads within two or moreblocks of threads have performed a barrier instruction and to causeperformance of one or more threads within the group of blocks of threadsto stop at least until all threads within the group of blocks haveperformed the barrier instruction. In at least one embodiment, graphicsmultiprocessor 4796 is used to perform an application programminginterface to cause memory to be shared between two or more groups ofblocks of threads.

In at least one embodiment, graphics multiprocessor 4796 is used toperform at least one aspect described with respect to example computersystem 100, example diagram 200, example diagram 300, example diagram400, example diagram 500, example process 600, example diagram 700,example application programming interface 800, example applicationprogramming interface 900, example diagram 1000, example diagram 1100,example application programming interface 1200, example applicationprogramming interface 1300, example computer system 1400, exampleapplication programming interface 1500, example diagram 1600, exampleapplication programming interface 1700, example computer system 1800,example application programming interface 1900, example computer system2000, example application programming interface 2100, example diagram2200, example diagram 2300, example diagram 2400, example diagram 2500,example application programming interface 2600, example diagram 2700,example diagram 2800, example diagram 2900, example applicationprogramming interface 3000, example application programming interface3100, example application programming interface 3200, example diagram3300, example application programming interface 3400, example softwarestack 3500, and/or other systems, methods, or operations describedherein.

FIG. 48 illustrates a graphics processor 4800, in accordance with atleast one embodiment. In at least one embodiment, graphics processor4800 includes a ring interconnect 4802, a pipeline front-end 4804, amedia engine 4837, and graphics cores 4880A-4880N. In at least oneembodiment, ring interconnect 4802 couples graphics processor 4800 toother processing units, including other graphics processors or one ormore general-purpose processor cores. In at least one embodiment,graphics processor 4800 is one of many processors integrated within amulti-core processing system.

In at least one embodiment, graphics processor 4800 receives batches ofcommands via ring interconnect 4802. In at least one embodiment,incoming commands are interpreted by a command streamer 4803 in pipelinefront-end 4804. In at least one embodiment, graphics processor 4800includes scalable execution logic to perform 3D geometry processing andmedia processing via graphics core(s) 4880A-4880N. In at least oneembodiment, for 3D geometry processing commands, command streamer 4803supplies commands to geometry pipeline 4836. In at least one embodiment,for at least some media processing commands, command streamer 4803supplies commands to a video front end 4834, which couples with a mediaengine 4837. In at least one embodiment, media engine 4837 includes aVideo Quality Engine (“VQE”) 4830 for video and image post-processingand a multi-format encode/decode (“MFX”) engine 4833 to providehardware-accelerated media data encode and decode. In at least oneembodiment, geometry pipeline 4836 and media engine 4837 each generateexecution threads for thread execution resources provided by at leastone graphics core 4880A.

In at least one embodiment, graphics processor 4800 includes scalablethread execution resources featuring modular graphics cores 4880A-4880N(sometimes referred to as core slices), each having multiple sub-cores4850A-550N, 4860A-4860N (sometimes referred to as core sub-slices). Inat least one embodiment, graphics processor 4800 can have any number ofgraphics cores 4880A through 4880N. In at least one embodiment, graphicsprocessor 4800 includes a graphics core 4880A having at least a firstsub-core 4850A and a second sub-core 4860A. In at least one embodiment,graphics processor 4800 is a low power processor with a single sub-core(e.g., sub-core 4850A). In at least one embodiment, graphics processor4800 includes multiple graphics cores 4880A-4880N, each including a setof first sub-cores 4850A-4850N and a set of second sub-cores4860A-4860N. In at least one embodiment, each sub-core in firstsub-cores 4850A-4850N includes at least a first set of execution units(“EUs”) 4852A-4852N and media/texture samplers 4854A-4854N. In at leastone embodiment, each sub-core in second sub-cores 4860A-4860N includesat least a second set of execution units 4862A-4862N and samplers4864A-4864N. In at least one embodiment, each sub-core 4850A-4850N,4860A-4860N shares a set of shared resources 4870A-4870N. In at leastone embodiment, shared resources 4870 include shared cache memory andpixel operation logic.

In at least one embodiment, at least one component shown or describedwith respect to FIG. 48 is used to implement techniques and/or functionsdescribed in connection with FIGS. 1-35 . In at least one embodiment,graphics processor 4800 is used to perform an application programminginterface to indicate two or more blocks of threads to be scheduled inparallel. In at least one embodiment, graphics processor 4800 is used toperform an application programming interface to determine which of twoor more blocks of threads to be scheduled in parallel. In at least oneembodiment, graphics processor 4800 is used to perform an applicationprogramming interface comprising one or more parameters to cause ascheduling policy of one or more blocks of one or more threads to beperformed. In at least one embodiment, graphics processor 4800 is usedto perform an application programming interface comprising one or moreparameters to indicate a scheduling policy of one or more blocks of oneor more threads. In at least one embodiment, graphics processor 4800 isused to perform an application programming interface to indicate amaximum number of blocks of threads capable of being scheduled inparallel. In at least one embodiment, graphics processor 4800 is used toperform an application programming interface comprising one or moreparameters to indicate one or more attributes of one or more groups ofblocks of one or more threads. In at least one embodiment, graphicsprocessor 4800 is used to perform an application programming interfaceto indicate a maximum number of blocks of threads to be scheduled inparallel. In at least one embodiment, graphics processor 4800 is used toperform an application programming interface to cause a kernel to begenerated to cause two or more blocks of two or more threads to bescheduled in parallel. In at least one embodiment, graphics processor4800 is used to perform an application programming interface comprisingone or more parameters to indicate one or more limitations of one ormore attributes of one or more groups of blocks of one or more threads.In at least one embodiment, graphics processor 4800 is used to performan application programming interface to indicate whether one or morethreads within two or more blocks of threads have performed a barrierinstruction. In at least one embodiment, graphics processor 4800 is usedto perform an application programming interface to cause performance ofone or more threads within a group of blocks of threads to stop at leastuntil all threads within the group of blocks have performed a barrierinstruction. In at least one embodiment, graphics processor 4800 is usedto perform an application programming interface to indicate whether oneor more threads within two or more blocks of threads have performed abarrier instruction and to cause performance of one or more threadswithin the group of blocks of threads to stop at least until all threadswithin the group of blocks have performed the barrier instruction. In atleast one embodiment, graphics processor 4800 is used to perform anapplication programming interface to cause memory to be shared betweentwo or more groups of blocks of threads.

In at least one embodiment, graphics processor 4800 is used to performat least one aspect described with respect to example computer system100, example diagram 200, example diagram 300, example diagram 400,example diagram 500, example process 600, example diagram 700, exampleapplication programming interface 800, example application programminginterface 900, example diagram 1000, example diagram 1100, exampleapplication programming interface 1200, example application programminginterface 1300, example computer system 1400, example applicationprogramming interface 1500, example diagram 1600, example applicationprogramming interface 1700, example computer system 1800, exampleapplication programming interface 1900, example computer system 2000,example application programming interface 2100, example diagram 2200,example diagram 2300, example diagram 2400, example diagram 2500,example application programming interface 2600, example diagram 2700,example diagram 2800, example diagram 2900, example applicationprogramming interface 3000, example application programming interface3100, example application programming interface 3200, example diagram3300, example application programming interface 3400, example softwarestack 3500, and/or other systems, methods, or operations describedherein.

FIG. 49 illustrates a processor 4900, in accordance with at least oneembodiment. In at least one embodiment, processor 4900 may include,without limitation, logic circuits to perform instructions. In at leastone embodiment, processor 4900 may perform instructions, including x86instructions, ARM instructions, specialized instructions for ASICs, etc.In at least one embodiment, processor 4910 may include registers tostore packed data, such as 64-bit wide MMX™ registers in microprocessorsenabled with MMX technology from Intel Corporation of Santa Clara, CalifIn at least one embodiment, MMX registers, available in both integer andfloating point forms, may operate with packed data elements thataccompany SIMD and streaming SIMD extensions (“SSE”) instructions. In atleast one embodiment, 128-bit wide XMM registers relating to SSE2, SSE3,SSE4, AVX, or beyond (referred to generically as “SSEx”) technology mayhold such packed data operands. In at least one embodiment, processors4910 may perform instructions to accelerate CUDA programs.

In at least one embodiment, processor 4900 includes an in-order frontend (“front end”) 4901 to fetch instructions to be executed and prepareinstructions to be used later in processor pipeline. In at least oneembodiment, front end 4901 may include several units. In at least oneembodiment, an instruction prefetcher 4926 fetches instructions frommemory and feeds instructions to an instruction decoder 4928 which inturn decodes or interprets instructions. For example, in at least oneembodiment, instruction decoder 4928 decodes a received instruction intoone or more operations called “micro-instructions” or “micro-operations”(also called “micro ops” or “uops”) for execution. In at least oneembodiment, instruction decoder 4928 parses instruction into an opcodeand corresponding data and control fields that may be used bymicro-architecture to perform operations. In at least one embodiment, atrace cache 4930 may assemble decoded uops into program orderedsequences or traces in a uop queue 4934 for execution. In at least oneembodiment, when trace cache 4930 encounters a complex instruction, amicrocode ROM 4932 provides uops needed to complete an operation.

In at least one embodiment, some instructions may be converted into asingle micro-op, whereas others need several micro-ops to complete fulloperation. In at least one embodiment, if more than four micro-ops areneeded to complete an instruction, instruction decoder 4928 may accessmicrocode ROM 4932 to perform instruction. In at least one embodiment,an instruction may be decoded into a small number of micro-ops forprocessing at instruction decoder 4928. In at least one embodiment, aninstruction may be stored within microcode ROM 4932 should a number ofmicro-ops be needed to accomplish operation. In at least one embodiment,trace cache 4930 refers to an entry point programmable logic array(“PLA”) to determine a correct micro-instruction pointer for readingmicrocode sequences to complete one or more instructions from microcodeROM 4932. In at least one embodiment, after microcode ROM 4932 finishessequencing micro-ops for an instruction, front end 4901 of machine mayresume fetching micro-ops from trace cache 4930.

In at least one embodiment, out-of-order execution engine (“out of orderengine”) 4903 may prepare instructions for execution. In at least oneembodiment, out-of-order execution logic has a number of buffers tosmooth out and re-order the flow of instructions to optimize performanceas they go down a pipeline and get scheduled for execution. Out-of-orderexecution engine 4903 includes, without limitation, anallocator/register renamer 4940, a memory uop queue 4942, aninteger/floating point uop queue 4944, a memory scheduler 4946, a fastscheduler 4902, a slow/general floating point scheduler (“slow/generalFP scheduler”) 4904, and a simple floating point scheduler (“simple FPscheduler”) 4906. In at least one embodiment, fast schedule 4902,slow/general floating point scheduler 4904, and simple floating pointscheduler 4906 are also collectively referred to herein as “uopschedulers 4902, 4904, 4906.” Allocator/register renamer 4940 allocatesmachine buffers and resources that each uop needs in order to execute.In at least one embodiment, allocator/register renamer 4940 renameslogic registers onto entries in a register file. In at least oneembodiment, allocator/register renamer 4940 also allocates an entry foreach uop in one of two uop queues, memory uop queue 4942 for memoryoperations and integer/floating point uop queue 4944 for non-memoryoperations, in front of memory scheduler 4946 and uop schedulers 4902,4904, 4906. In at least one embodiment, uop schedulers 4902, 4904, 4906,determine when a uop is ready to execute based on readiness of theirdependent input register operand sources and availability of executionresources uops need to complete their operation. In at least oneembodiment, fast scheduler 4902 of at least one embodiment may scheduleon each half of main clock cycle while slow/general floating pointscheduler 4904 and simple floating point scheduler 4906 may scheduleonce per main processor clock cycle. In at least one embodiment, uopschedulers 4902, 4904, 4906 arbitrate for dispatch ports to scheduleuops for execution.

In at least one embodiment, execution block 4911 includes, withoutlimitation, an integer register file/bypass network 4908, a floatingpoint register file/bypass network (“FP register file/bypass network”)4910, address generation units (“AGUs”) 4912 and 4914, fast ALUs 4916and 4918, a slow ALU 4920, a floating point ALU (“FP”) 4922, and afloating point move unit (“FP move”) 4924. In at least one embodiment,integer register file/bypass network 4908 and floating point registerfile/bypass network 4910 are also referred to herein as “register files4908, 4910.” In at least one embodiment, AGUSs 4912 and 4914, fast ALUs4916 and 4918, slow ALU 4920, floating point ALU 4922, and floatingpoint move unit 4924 are also referred to herein as “execution units4912, 4914, 4916, 4918, 4920, 4922, and 4924.” In at least oneembodiment, an execution block may include, without limitation, anynumber (including zero) and type of register files, bypass networks,address generation units, and execution units, in any combination.

In at least one embodiment, register files 4908, 4910 may be arrangedbetween uop schedulers 4902, 4904, 4906, and execution units 4912, 4914,4916, 4918, 4920, 4922, and 4924. In at least one embodiment, integerregister file/bypass network 4908 performs integer operations. In atleast one embodiment, floating point register file/bypass network 4910performs floating point operations. In at least one embodiment, each ofregister files 4908, 4910 may include, without limitation, a bypassnetwork that may bypass or forward just completed results that have notyet been written into register file to new dependent uops. In at leastone embodiment, register files 4908, 4910 may communicate data with eachother. In at least one embodiment, integer register file/bypass network4908 may include, without limitation, two separate register files, oneregister file for low-order thirty-two bits of data and a secondregister file for high order thirty-two bits of data. In at least oneembodiment, floating point register file/bypass network 4910 mayinclude, without limitation, 128-bit wide entries because floating pointinstructions typically have operands from 64 to 128 bits in width.

In at least one embodiment, execution units 4912, 4914, 4916, 4918,4920, 4922, 4924 may execute instructions. In at least one embodiment,register files 4908, 4910 store integer and floating point data operandvalues that micro-instructions need to execute. In at least oneembodiment, processor 4900 may include, without limitation, any numberand combination of execution units 4912, 4914, 4916, 4918, 4920, 4922,4924. In at least one embodiment, floating point ALU 4922 and floatingpoint move unit 4924 may execute floating point, MMX, SIMD, AVX and SSE,or other operations. In at least one embodiment, floating point ALU 4922may include, without limitation, a 64-bit by 64-bit floating pointdivider to execute divide, square root, and remainder micro ops. In atleast one embodiment, instructions involving a floating point value maybe handled with floating point hardware. In at least one embodiment, ALUoperations may be passed to fast ALUs 4916, 4918. In at least oneembodiment, fast ALUS 4916, 4918 may execute fast operations with aneffective latency of half a clock cycle. In at least one embodiment,most complex integer operations go to slow ALU 4920 as slow ALU 4920 mayinclude, without limitation, integer execution hardware for long-latencytype of operations, such as a multiplier, shifts, flag logic, and branchprocessing. In at least one embodiment, memory load/store operations maybe executed by AGUs 4912, 4914. In at least one embodiment, fast ALU4916, fast ALU 4918, and slow ALU 4920 may perform integer operations on64-bit data operands. In at least one embodiment, fast ALU 4916, fastALU 4918, and slow ALU 4920 may be implemented to support a variety ofdata bit sizes including sixteen, thirty-two, 128, 256, etc. In at leastone embodiment, floating point ALU 4922 and floating point move unit4924 may be implemented to support a range of operands having bits ofvarious widths. In at least one embodiment, floating point ALU 4922 andfloating point move unit 4924 may operate on 128-bit wide packed dataoperands in conjunction with SIMD and multimedia instructions.

In at least one embodiment, uop schedulers 4902, 4904, 4906 dispatchdependent operations before parent load has finished executing. In atleast one embodiment, as uops may be speculatively scheduled andexecuted in processor 4900, processor 4900 may also include logic tohandle memory misses. In at least one embodiment, if a data load missesin a data cache, there may be dependent operations in flight in pipelinethat have left a scheduler with temporarily incorrect data. In at leastone embodiment, a replay mechanism tracks and re-executes instructionsthat use incorrect data. In at least one embodiment, dependentoperations might need to be replayed and independent ones may be allowedto complete. In at least one embodiment, schedulers and replaymechanisms of at least one embodiment of a processor may also bedesigned to catch instruction sequences for text string comparisonoperations.

In at least one embodiment, the term “registers” may refer to on-boardprocessor storage locations that may be used as part of instructions toidentify operands. In at least one embodiment, registers may be thosethat may be usable from outside of a processor (from a programmer'sperspective). In at least one embodiment, registers might not be limitedto a particular type of circuit. Rather, in at least one embodiment, aregister may store data, provide data, and perform functions describedherein. In at least one embodiment, registers described herein may beimplemented by circuitry within a processor using any number ofdifferent techniques, such as dedicated physical registers, dynamicallyallocated physical registers using register renaming, combinations ofdedicated and dynamically allocated physical registers, etc. In at leastone embodiment, integer registers store 32-bit integer data. A registerfile of at least one embodiment also contains eight multimedia SIMDregisters for packed data.

In at least one embodiment, at least one component shown or describedwith respect to FIG. 49 is used to implement techniques and/or functionsdescribed in connection with FIGS. 1-35 . In at least one embodiment,processor 4900 is used to perform an application programming interfaceto indicate two or more blocks of threads to be scheduled in parallel.In at least one embodiment, processor 4900 is used to perform anapplication programming interface to determine which of two or moreblocks of threads to be scheduled in parallel. In at least oneembodiment, processor 4900 is used to perform an application programminginterface comprising one or more parameters to cause a scheduling policyof one or more blocks of one or more threads to be performed. In atleast one embodiment, processor 4900 is used to perform an applicationprogramming interface comprising one or more parameters to indicate ascheduling policy of one or more blocks of one or more threads. In atleast one embodiment, processor 4900 is used to perform an applicationprogramming interface to indicate a maximum number of blocks of threadscapable of being scheduled in parallel. In at least one embodiment,processor 4900 is used to perform an application programming interfacecomprising one or more parameters to indicate one or more attributes ofone or more groups of blocks of one or more threads. In at least oneembodiment, processor 4900 is used to perform an application programminginterface to indicate a maximum number of blocks of threads to bescheduled in parallel. In at least one embodiment, processor 4900 isused to perform an application programming interface to cause a kernelto be generated to cause two or more blocks of two or more threads to bescheduled in parallel. In at least one embodiment, processor 4900 isused to perform an application programming interface comprising one ormore parameters to indicate one or more limitations of one or moreattributes of one or more groups of blocks of one or more threads. In atleast one embodiment, processor 4900 is used to perform an applicationprogramming interface to indicate whether one or more threads within twoor more blocks of threads have performed a barrier instruction. In atleast one embodiment, processor 4900 is used to perform an applicationprogramming interface to cause performance of one or more threads withina group of blocks of threads to stop at least until all threads withinthe group of blocks have performed a barrier instruction. In at leastone embodiment, processor 4900 is used to perform an applicationprogramming interface to indicate whether one or more threads within twoor more blocks of threads have performed a barrier instruction and tocause performance of one or more threads within the group of blocks ofthreads to stop at least until all threads within the group of blockshave performed the barrier instruction. In at least one embodiment,processor 4900 is used to perform an application programming interfaceto cause memory to be shared between two or more groups of blocks ofthreads.

In at least one embodiment, processor 4900 is used to perform at leastone aspect described with respect to example computer system 100,example diagram 200, example diagram 300, example diagram 400, examplediagram 500, example process 600, example diagram 700, exampleapplication programming interface 800, example application programminginterface 900, example diagram 1000, example diagram 1100, exampleapplication programming interface 1200, example application programminginterface 1300, example computer system 1400, example applicationprogramming interface 1500, example diagram 1600, example applicationprogramming interface 1700, example computer system 1800, exampleapplication programming interface 1900, example computer system 2000,example application programming interface 2100, example diagram 2200,example diagram 2300, example diagram 2400, example diagram 2500,example application programming interface 2600, example diagram 2700,example diagram 2800, example diagram 2900, example applicationprogramming interface 3000, example application programming interface3100, example application programming interface 3200, example diagram3300, example application programming interface 3400, example softwarestack 3500, and/or other systems, methods, or operations describedherein.

FIG. 50 illustrates a processor 5000, in accordance with at least oneembodiment. In at least one embodiment, processor 5000 includes, withoutlimitation, one or more processor cores (“cores”) 5002A-5002N, anintegrated memory controller 5014, and an integrated graphics processor5008. In at least one embodiment, processor 5000 can include additionalcores up to and including additional processor core 5002N represented bydashed lined boxes. In at least one embodiment, each of processor cores5002A-5002N includes one or more internal cache units 5004A-5004N. In atleast one embodiment, each processor core also has access to one or moreshared cached units 5006.

In at least one embodiment, internal cache units 5004A-5004N and sharedcache units 5006 represent a cache memory hierarchy within processor5000. In at least one embodiment, cache memory units 5004A-5004N mayinclude at least one level of instruction and data cache within eachprocessor core and one or more levels of shared mid-level cache, such asan L2, L3, Level 4 (“L4”), or other levels of cache, where a highestlevel of cache before external memory is classified as an LLC. In atleast one embodiment, cache coherency logic maintains coherency betweenvarious cache units 5006 and 5004A-5004N.

In at least one embodiment, processor 5000 may also include a set of oneor more bus controller units 5016 and a system agent core 5010. In atleast one embodiment, one or more bus controller units 5016 manage a setof peripheral buses, such as one or more PCI or PCI express buses. In atleast one embodiment, system agent core 5010 provides managementfunctionality for various processor components. In at least oneembodiment, system agent core 5010 includes one or more integratedmemory controllers 5014 to manage access to various external memorydevices (not shown).

In at least one embodiment, one or more of processor cores 5002A-5002Ninclude support for simultaneous multi-threading. In at least oneembodiment, system agent core 5010 includes components for coordinatingand operating processor cores 5002A-5002N during multi-threadedprocessing. In at least one embodiment, system agent core 5010 mayadditionally include a power control unit (“PCU”), which includes logicand components to regulate one or more power states of processor cores5002A-5002N and graphics processor 5008.

In at least one embodiment, processor 5000 additionally includesgraphics processor 5008 to execute graphics processing operations. In atleast one embodiment, graphics processor 5008 couples with shared cacheunits 5006, and system agent core 5010, including one or more integratedmemory controllers 5014. In at least one embodiment, system agent core5010 also includes a display controller 5011 to drive graphics processoroutput to one or more coupled displays. In at least one embodiment,display controller 5011 may also be a separate module coupled withgraphics processor 5008 via at least one interconnect, or may beintegrated within graphics processor 5008.

In at least one embodiment, a ring based interconnect unit 5012 is usedto couple internal components of processor 5000. In at least oneembodiment, an alternative interconnect unit may be used, such as apoint-to-point interconnect, a switched interconnect, or othertechniques. In at least one embodiment, graphics processor 5008 coupleswith ring interconnect 5012 via an I/O link 5013.

In at least one embodiment, I/O link 5013 represents at least one ofmultiple varieties of I/O interconnects, including an on package I/Ointerconnect which facilitates communication between various processorcomponents and a high-performance embedded memory module 5018, such asan eDRAM module. In at least one embodiment, each of processor cores5002A-5002N and graphics processor 5008 use embedded memory modules 5018as a shared LLC.

In at least one embodiment, processor cores 5002A-5002N are homogeneouscores executing a common instruction set architecture. In at least oneembodiment, processor cores 5002A-5002N are heterogeneous in terms ofISA, where one or more of processor cores 5002A-5002N execute a commoninstruction set, while one or more other cores of processor cores5002A-50-02N executes a subset of a common instruction set or adifferent instruction set. In at least one embodiment, processor cores5002A-5002N are heterogeneous in terms of microarchitecture, where oneor more cores having a relatively higher power consumption couple withone or more cores having a lower power consumption. In at least oneembodiment, processor 5000 can be implemented on one or more chips or asan SoC integrated circuit.

In at least one embodiment, at least one component shown or describedwith respect to FIG. 50 is used to implement techniques and/or functionsdescribed in connection with FIGS. 1-35 . In at least one embodiment, atleast one of processor 5000 or graphics processor 5008 is used toperform an application programming interface to indicate two or moreblocks of threads to be scheduled in parallel. In at least oneembodiment, at least one of processor 5000 or graphics processor 5008 isused to perform an application programming interface to determine whichof two or more blocks of threads to be scheduled in parallel. In atleast one embodiment, at least one of processor 5000 or graphicsprocessor 5008 is used to perform an application programming interfacecomprising one or more parameters to cause a scheduling policy of one ormore blocks of one or more threads to be performed. In at least oneembodiment, at least one of processor 5000 or graphics processor 5008 isused to perform an application programming interface comprising one ormore parameters to indicate a scheduling policy of one or more blocks ofone or more threads. In at least one embodiment, at least one ofprocessor 5000 or graphics processor 5008 is used to perform anapplication programming interface to indicate a maximum number of blocksof threads capable of being scheduled in parallel. In at least oneembodiment, at least one of processor 5000 or graphics processor 5008 isused to perform an application programming interface comprising one ormore parameters to indicate one or more attributes of one or more groupsof blocks of one or more threads. In at least one embodiment, at leastone of processor 5000 or graphics processor 5008 is used to perform anapplication programming interface to indicate a maximum number of blocksof threads to be scheduled in parallel. In at least one embodiment, atleast one of processor 5000 or graphics processor 5008 is used toperform an application programming interface to cause a kernel to begenerated to cause two or more blocks of two or more threads to bescheduled in parallel. In at least one embodiment, at least one ofprocessor 5000 or graphics processor 5008 is used to perform anapplication programming interface comprising one or more parameters toindicate one or more limitations of one or more attributes of one ormore groups of blocks of one or more threads. In at least oneembodiment, at least one of processor 5000 or graphics processor 5008 isused to perform an application programming interface to indicate whetherone or more threads within two or more blocks of threads have performeda barrier instruction. In at least one embodiment, at least one ofprocessor 5000 or graphics processor 5008 is used to perform anapplication programming interface to cause performance of one or morethreads within a group of blocks of threads to stop at least until allthreads within the group of blocks have performed a barrier instruction.In at least one embodiment, at least one of processor 5000 or graphicsprocessor 5008 is used to perform an application programming interfaceto indicate whether one or more threads within two or more blocks ofthreads have performed a barrier instruction and to cause performance ofone or more threads within the group of blocks of threads to stop atleast until all threads within the group of blocks have performed thebarrier instruction. In at least one embodiment, at least one ofprocessor 5000 or graphics processor 5008 is used to perform anapplication programming interface to cause memory to be shared betweentwo or more groups of blocks of threads.

In at least one embodiment, at least one of processor 5000 or graphicsprocessor 5008 is used to perform at least one aspect described withrespect to example computer system 100, example diagram 200, examplediagram 300, example diagram 400, example diagram 500, example process600, example diagram 700, example application programming interface 800,example application programming interface 900, example diagram 1000,example diagram 1100, example application programming interface 1200,example application programming interface 1300, example computer system1400, example application programming interface 1500, example diagram1600, example application programming interface 1700, example computersystem 1800, example application programming interface 1900, examplecomputer system 2000, example application programming interface 2100,example diagram 2200, example diagram 2300, example diagram 2400,example diagram 2500, example application programming interface 2600,example diagram 2700, example diagram 2800, example diagram 2900,example application programming interface 3000, example applicationprogramming interface 3100, example application programming interface3200, example diagram 3300, example application programming interface3400, example software stack 3500, and/or other systems, methods, oroperations described herein.

FIG. 51 illustrates a graphics processor core 5100, in accordance withat least one embodiment described. In at least one embodiment, graphicsprocessor core 5100 is included within a graphics core array. In atleast one embodiment, graphics processor core 5100, sometimes referredto as a core slice, can be one or multiple graphics cores within amodular graphics processor. In at least one embodiment, graphicsprocessor core 5100 is exemplary of one graphics core slice, and agraphics processor as described herein may include multiple graphicscore slices based on target power and performance envelopes. In at leastone embodiment, each graphics core 5100 can include a fixed functionblock 5130 coupled with multiple sub-cores 5101A-5101F, also referred toas sub-slices, that include modular blocks of general-purpose and fixedfunction logic.

In at least one embodiment, fixed function block 5130 includes ageometry/fixed function pipeline 5136 that can be shared by allsub-cores in graphics processor 5100, for example, in lower performanceand/or lower power graphics processor implementations. In at least oneembodiment, geometry/fixed function pipeline 5136 includes a 3D fixedfunction pipeline, a video front-end unit, a thread spawner and threaddispatcher, and a unified return buffer manager, which manages unifiedreturn buffers.

In at least one embodiment, fixed function block 5130 also includes agraphics SoC interface 5137, a graphics microcontroller 5138, and amedia pipeline 5139. Graphics SoC interface 5137 provides an interfacebetween graphics core 5100 and other processor cores within an SoCintegrated circuit. In at least one embodiment, graphics microcontroller5138 is a programmable sub-processor that is configurable to managevarious functions of graphics processor 5100, including thread dispatch,scheduling, and pre-emption. In at least one embodiment, media pipeline5139 includes logic to facilitate decoding, encoding, pre-processing,and/or post-processing of multimedia data, including image and videodata. In at least one embodiment, media pipeline 5139 implements mediaoperations via requests to compute or sampling logic within sub-cores5101-5101F.

In at least one embodiment, SoC interface 5137 enables graphics core5100 to communicate with general-purpose application processor cores(e.g., CPUs) and/or other components within an SoC, including memoryhierarchy elements such as a shared LLC memory, system RAM, and/orembedded on-chip or on-package DRAM. In at least one embodiment, SoCinterface 5137 can also enable communication with fixed function deviceswithin an SoC, such as camera imaging pipelines, and enables use ofand/or implements global memory atomics that may be shared betweengraphics core 5100 and CPUs within an SoC. In at least one embodiment,SoC interface 5137 can also implement power management controls forgraphics core 5100 and enable an interface between a clock domain ofgraphic core 5100 and other clock domains within an SoC. In at least oneembodiment, SoC interface 5137 enables receipt of command buffers from acommand streamer and global thread dispatcher that are configured toprovide commands and instructions to each of one or more graphics coreswithin a graphics processor. In at least one embodiment, commands andinstructions can be dispatched to media pipeline 5139, when mediaoperations are to be performed, or a geometry and fixed functionpipeline (e.g., geometry and fixed function pipeline 5136, geometry andfixed function pipeline 5114) when graphics processing operations are tobe performed.

In at least one embodiment, graphics microcontroller 5138 can beconfigured to perform various scheduling and management tasks forgraphics core 5100. In at least one embodiment, graphics microcontroller5138 can perform graphics and/or compute workload scheduling on variousgraphics parallel engines within execution unit (EU) arrays 5102A-5102F,5104A-5104F within sub-cores 5101A-5101F. In at least one embodiment,host software executing on a CPU core of an SoC including graphics core5100 can submit workloads one of multiple graphic processor doorbells,which invokes a scheduling operation on an appropriate graphics engine.In at least one embodiment, scheduling operations include determiningwhich workload to run next, submitting a workload to a command streamer,pre-empting existing workloads running on an engine, monitoring progressof a workload, and notifying host software when a workload is complete.In at least one embodiment, graphics microcontroller 5138 can alsofacilitate low-power or idle states for graphics core 5100, providinggraphics core 5100 with an ability to save and restore registers withingraphics core 5100 across low-power state transitions independently froman operating system and/or graphics driver software on a system.

In at least one embodiment, graphics core 5100 may have greater than orfewer than illustrated sub-cores 5101A-5101F, up to N modular sub-cores.For each set of N sub-cores, in at least one embodiment, graphics core5100 can also include shared function logic 5110, shared and/or cachememory 5112, a geometry/fixed function pipeline 5114, as well asadditional fixed function logic 5116 to accelerate various graphics andcompute processing operations. In at least one embodiment, sharedfunction logic 5110 can include logic units (e.g., sampler, math, and/orinter-thread communication logic) that can be shared by each N sub-coreswithin graphics core 5100. Shared and/or cache memory 5112 can be an LLCfor N sub-cores 5101A-5101F within graphics core 5100 and can also serveas shared memory that is accessible by multiple sub-cores. In at leastone embodiment, geometry/fixed function pipeline 5114 can be includedinstead of geometry/fixed function pipeline 5136 within fixed functionblock 5130 and can include same or similar logic units.

In at least one embodiment, graphics core 5100 includes additional fixedfunction logic 5116 that can include various fixed function accelerationlogic for use by graphics core 5100. In at least one embodiment,additional fixed function logic 5116 includes an additional geometrypipeline for use in position only shading. In position-only shading, atleast two geometry pipelines exist, whereas in a full geometry pipelinewithin geometry/fixed function pipeline 5116, 5136, and a cull pipeline,which is an additional geometry pipeline which may be included withinadditional fixed function logic 5116. In at least one embodiment, cullpipeline is a trimmed down version of a full geometry pipeline. In atleast one embodiment, a full pipeline and a cull pipeline can executedifferent instances of an application, each instance having a separatecontext. In at least one embodiment, position only shading can hide longcull runs of discarded triangles, enabling shading to be completedearlier in some instances. For example, in at least one embodiment, cullpipeline logic within additional fixed function logic 5116 can executeposition shaders in parallel with a main application and generallygenerates critical results faster than a full pipeline, as a cullpipeline fetches and shades position attribute of vertices, withoutperforming rasterization and rendering of pixels to a frame buffer. Inat least one embodiment, a cull pipeline can use generated criticalresults to compute visibility information for all triangles withoutregard to whether those triangles are culled. In at least oneembodiment, a full pipeline (which in this instance may be referred toas a replay pipeline) can consume visibility information to skip culledtriangles to shade only visible triangles that are finally passed to arasterization phase.

In at least one embodiment, additional fixed function logic 5116 canalso include general purpose processing acceleration logic, such asfixed function matrix multiplication logic, for accelerating CUDAprograms.

In at least one embodiment, each graphics sub-core 5101A-5101F includesa set of execution resources that may be used to perform graphics,media, and compute operations in response to requests by graphicspipeline, media pipeline, or shader programs. In at least oneembodiment, graphics sub-cores 5101A-5101F include multiple EU arrays5102A-5102F, 5104A-5104F, thread dispatch and inter-thread communication(“TD/IC”) logic 5103A-5103F, a 3D (e.g., texture) sampler 5105A-5105F, amedia sampler 5106A-5106F, a shader processor 5107A-5107F, and sharedlocal memory (“SLM”) 5108A-5108F. EU arrays 5102A-5102F, 5104A-5104Feach include multiple execution units, which are GPGPUs capable ofperforming floating-point and integer/fixed-point logic operations inservice of a graphics, media, or compute operation, including graphics,media, or compute shader programs. In at least one embodiment, TD/IClogic 5103A-5103F performs local thread dispatch and thread controloperations for execution units within a sub-core and facilitatecommunication between threads executing on execution units of asub-core. In at least one embodiment, 3D sampler 5105A-5105F can readtexture or other 3D graphics related data into memory. In at least oneembodiment, 3D sampler can read texture data differently based on aconfigured sample state and texture format associated with a giventexture. In at least one embodiment, media sampler 5106A-5106F canperform similar read operations based on a type and format associatedwith media data. In at least one embodiment, each graphics sub-core5101A-5101F can alternately include a unified 3D and media sampler. Inat least one embodiment, threads executing on execution units withineach of sub-cores 5101A-5101F can make use of shared local memory5108A-5108F within each sub-core, to enable threads executing within athread group to execute using a common pool of on-chip memory.

In at least one embodiment, at least one component shown or describedwith respect to FIG. 51 is used to implement techniques and/or functionsdescribed in connection with FIGS. 1-35 . In at least one embodiment,graphics processor core 5100 is used to perform an applicationprogramming interface to indicate two or more blocks of threads to bescheduled in parallel. In at least one embodiment, graphics processorcore 5100 is used to perform an application programming interface todetermine which of two or more blocks of threads to be scheduled inparallel. In at least one embodiment, graphics processor core 5100 isused to perform an application programming interface comprising one ormore parameters to cause a scheduling policy of one or more blocks ofone or more threads to be performed. In at least one embodiment,graphics processor core 5100 is used to perform an applicationprogramming interface comprising one or more parameters to indicate ascheduling policy of one or more blocks of one or more threads. In atleast one embodiment, graphics processor core 5100 is used to perform anapplication programming interface to indicate a maximum number of blocksof threads capable of being scheduled in parallel. In at least oneembodiment, graphics processor core 5100 is used to perform anapplication programming interface comprising one or more parameters toindicate one or more attributes of one or more groups of blocks of oneor more threads. In at least one embodiment, graphics processor core5100 is used to perform an application programming interface to indicatea maximum number of blocks of threads to be scheduled in parallel. In atleast one embodiment, graphics processor core 5100 is used to perform anapplication programming interface to cause a kernel to be generated tocause two or more blocks of two or more threads to be scheduled inparallel. In at least one embodiment, graphics processor core 5100 isused to perform an application programming interface comprising one ormore parameters to indicate one or more limitations of one or moreattributes of one or more groups of blocks of one or more threads. In atleast one embodiment, graphics processor core 5100 is used to perform anapplication programming interface to indicate whether one or morethreads within two or more blocks of threads have performed a barrierinstruction. In at least one embodiment, graphics processor core 5100 isused to perform an application programming interface to causeperformance of one or more threads within a group of blocks of threadsto stop at least until all threads within the group of blocks haveperformed a barrier instruction. In at least one embodiment, graphicsprocessor core 5100 is used to perform an application programminginterface to indicate whether one or more threads within two or moreblocks of threads have performed a barrier instruction and to causeperformance of one or more threads within the group of blocks of threadsto stop at least until all threads within the group of blocks haveperformed the barrier instruction. In at least one embodiment, graphicsprocessor core 5100 is used to perform an application programminginterface to cause memory to be shared between two or more groups ofblocks of threads.

In at least one embodiment, graphics processor core 5100 is used toperform at least one aspect described with respect to example computersystem 100, example diagram 200, example diagram 300, example diagram400, example diagram 500, example process 600, example diagram 700,example application programming interface 800, example applicationprogramming interface 900, example diagram 1000, example diagram 1100,example application programming interface 1200, example applicationprogramming interface 1300, example computer system 1400, exampleapplication programming interface 1500, example diagram 1600, exampleapplication programming interface 1700, example computer system 1800,example application programming interface 1900, example computer system2000, example application programming interface 2100, example diagram2200, example diagram 2300, example diagram 2400, example diagram 2500,example application programming interface 2600, example diagram 2700,example diagram 2800, example diagram 2900, example applicationprogramming interface 3000, example application programming interface3100, example application programming interface 3200, example diagram3300, example application programming interface 3400, example softwarestack 3500, and/or other systems, methods, or operations describedherein.

FIG. 52 illustrates a parallel processing unit (“PPU”) 5200, inaccordance with at least one embodiment. In at least one embodiment, PPU5200 is configured with machine-readable code that, if executed by PPU5200, causes PPU 5200 to perform some or all of processes and techniquesdescribed herein. In at least one embodiment, PPU 5200 is amulti-threaded processor that is implemented on one or more integratedcircuit devices and that utilizes multithreading as a latency-hidingtechnique designed to process computer-readable instructions (alsoreferred to as machine-readable instructions or simply instructions) onmultiple threads in parallel. In at least one embodiment, a threadrefers to a thread of execution and is an instantiation of a set ofinstructions configured to be executed by PPU 5200. In at least oneembodiment, PPU 5200 is a GPU configured to implement a graphicsrendering pipeline for processing three-dimensional (“3D”) graphics datain order to generate two-dimensional (“2D”) image data for display on adisplay device such as an LCD device. In at least one embodiment, PPU5200 is utilized to perform computations such as linear algebraoperations and machine-learning operations. FIG. 52 illustrates anexample parallel processor for illustrative purposes only and should beconstrued as a non-limiting example of a processor architecture that maybe implemented in at least one embodiment.

In at least one embodiment, one or more PPUs 5200 are configured toaccelerate High Performance Computing (“HPC”), data center, and machinelearning applications. In at least one embodiment, one or more PPUs 5200are configured to accelerate CUDA programs. In at least one embodiment,PPU 5200 includes, without limitation, an I/O unit 5206, a front-endunit 5210, a scheduler unit 5212, a work distribution unit 5214, a hub5216, a crossbar (“Xbar”) 5220, one or more general processing clusters(“GPCs”) 5218, and one or more partition units (“memory partitionunits”) 5222. In at least one embodiment, PPU 5200 is connected to ahost processor or other PPUs 5200 via one or more high-speed GPUinterconnects (“GPU interconnects”) 5208. In at least one embodiment,PPU 5200 is connected to a host processor or other peripheral devicesvia a system bus or interconnect 5202. In at least one embodiment, PPU5200 is connected to a local memory comprising one or more memorydevices (“memory”) 5204. In at least one embodiment, memory devices 5204include, without limitation, one or more dynamic random access memory(DRAM) devices. In at least one embodiment, one or more DRAM devices areconfigured and/or configurable as high-bandwidth memory (“HBM”)subsystems, with multiple DRAM dies stacked within each device.

In at least one embodiment, high-speed GPU interconnect 5208 may referto a wire-based multi-lane communications link that is used by systemsto scale and include one or more PPUs 5200 combined with one or moreCPUs, supports cache coherence between PPUs 5200 and CPUs, and CPUmastering. In at least one embodiment, data and/or commands aretransmitted by high-speed GPU interconnect 5208 through hub 5216 to/fromother units of PPU 5200 such as one or more copy engines, videoencoders, video decoders, power management units, and other componentswhich may not be explicitly illustrated in FIG. 52 .

In at least one embodiment, I/O unit 5206 is configured to transmit andreceive communications (e.g., commands, data) from a host processor (notillustrated in FIG. 52 ) over system bus 5202. In at least oneembodiment, I/O unit 5206 communicates with host processor directly viasystem bus 5202 or through one or more intermediate devices such as amemory bridge. In at least one embodiment, I/O unit 5206 may communicatewith one or more other processors, such as one or more of PPUs 5200 viasystem bus 5202. In at least one embodiment, I/O unit 5206 implements aPCIe interface for communications over a PCIe bus. In at least oneembodiment, I/O unit 5206 implements interfaces for communicating withexternal devices.

In at least one embodiment, I/O unit 5206 decodes packets received viasystem bus 5202. In at least one embodiment, at least some packetsrepresent commands configured to cause PPU 5200 to perform variousoperations. In at least one embodiment, I/O unit 5206 transmits decodedcommands to various other units of PPU 5200 as specified by commands. Inat least one embodiment, commands are transmitted to front-end unit 5210and/or transmitted to hub 5216 or other units of PPU 5200 such as one ormore copy engines, a video encoder, a video decoder, a power managementunit, etc. (not explicitly illustrated in FIG. 52 ). In at least oneembodiment, I/O unit 5206 is configured to route communications betweenand among various logical units of PPU 5200.

In at least one embodiment, a program executed by host processor encodesa command stream in a buffer that provides workloads to PPU 5200 forprocessing. In at least one embodiment, a workload comprisesinstructions and data to be processed by those instructions. In at leastone embodiment, buffer is a region in a memory that is accessible (e.g.,read/write) by both a host processor and PPU 5200—a host interface unitmay be configured to access buffer in a system memory connected tosystem bus 5202 via memory requests transmitted over system bus 5202 byI/O unit 5206. In at least one embodiment, a host processor writes acommand stream to a buffer and then transmits a pointer to the start ofthe command stream to PPU 5200 such that front-end unit 5210 receivespointers to one or more command streams and manages one or more commandstreams, reading commands from command streams and forwarding commandsto various units of PPU 5200.

In at least one embodiment, front-end unit 5210 is coupled to schedulerunit 5212 that configures various GPCs 5218 to process tasks defined byone or more command streams. In at least one embodiment, scheduler unit5212 is configured to track state information related to various tasksmanaged by scheduler unit 5212 where state information may indicatewhich of GPCs 5218 a task is assigned to, whether task is active orinactive, a priority level associated with task, and so forth. In atleast one embodiment, scheduler unit 5212 manages execution of aplurality of tasks on one or more of GPCs 5218.

In at least one embodiment, scheduler unit 5212 is coupled to workdistribution unit 5214 that is configured to dispatch tasks forexecution on GPCs 5218. In at least one embodiment, work distributionunit 5214 tracks a number of scheduled tasks received from schedulerunit 5212 and work distribution unit 5214 manages a pending task pooland an active task pool for each of GPCs 5218. In at least oneembodiment, pending task pool comprises a number of slots (e.g., 32slots) that contain tasks assigned to be processed by a particular GPC5218; active task pool may comprise a number of slots (e.g., 4 slots)for tasks that are actively being processed by GPCs 5218 such that asone of GPCs 5218 completes execution of a task, that task is evictedfrom active task pool for GPC 5218 and one of other tasks from pendingtask pool is selected and scheduled for execution on GPC 5218. In atleast one embodiment, if an active task is idle on GPC 5218, such aswhile waiting for a data dependency to be resolved, then the active taskis evicted from GPC 5218 and returned to a pending task pool whileanother task in the pending task pool is selected and scheduled forexecution on GPC 5218.

In at least one embodiment, work distribution unit 5214 communicateswith one or more GPCs 5218 via XBar 5220. In at least one embodiment,XBar 5220 is an interconnect network that couples many units of PPU 5200to other units of PPU 5200 and can be configured to couple workdistribution unit 5214 to a particular GPC 5218. In at least oneembodiment, one or more other units of PPU 5200 may also be connected toXBar 5220 via hub 5216.

In at least one embodiment, tasks are managed by scheduler unit 5212 anddispatched to one of GPCs 5218 by work distribution unit 5214. GPC 5218is configured to process task and generate results. In at least oneembodiment, results may be consumed by other tasks within GPC 5218,routed to a different GPC 5218 via XBar 5220, or stored in memory 5204.In at least one embodiment, results can be written to memory 5204 viapartition units 5222, which implement a memory interface for reading andwriting data to/from memory 5204. In at least one embodiment, resultscan be transmitted to another PPU 5204 or CPU via high-speed GPUinterconnect 5208. In at least one embodiment, PPU 5200 includes,without limitation, a number U of partition units 5222 that is equal tonumber of separate and distinct memory devices 5204 coupled to PPU 5200.

In at least one embodiment, a host processor executes a driver kernelthat implements an application programming interface (“API”) thatenables one or more applications executing on host processor to scheduleoperations for execution on PPU 5200. In at least one embodiment,multiple compute applications are simultaneously executed by PPU 5200and PPU 5200 provides isolation, quality of service (“QoS”), andindependent address spaces for multiple compute applications. In atleast one embodiment, an application generates instructions (e.g., inthe form of API calls) that cause a driver kernel to generate one ormore tasks for execution by PPU 5200 and the driver kernel outputs tasksto one or more streams being processed by PPU 5200. In at least oneembodiment, each task comprises one or more groups of related threads,which may be referred to as a warp. In at least one embodiment, a warpcomprises a plurality of related threads (e.g., 32 threads) that can beexecuted in parallel. In at least one embodiment, cooperating threadscan refer to a plurality of threads including instructions to perform atask and that exchange data through shared memory.

In at least one embodiment, at least one component shown or describedwith respect to FIG. 52 is used to implement techniques and/or functionsdescribed in connection with FIGS. 1-35 . In at least one embodiment,parallel processing unit 5200 is used to perform an applicationprogramming interface to indicate two or more blocks of threads to bescheduled in parallel. In at least one embodiment, parallel processingunit 5200 is used to perform an application programming interface todetermine which of two or more blocks of threads to be scheduled inparallel. In at least one embodiment, parallel processing unit 5200 isused to perform an application programming interface comprising one ormore parameters to cause a scheduling policy of one or more blocks ofone or more threads to be performed. In at least one embodiment,parallel processing unit 5200 is used to perform an applicationprogramming interface comprising one or more parameters to indicate ascheduling policy of one or more blocks of one or more threads. In atleast one embodiment, parallel processing unit 5200 is used to performan application programming interface to indicate a maximum number ofblocks of threads capable of being scheduled in parallel. In at leastone embodiment, parallel processing unit 5200 is used to perform anapplication programming interface comprising one or more parameters toindicate one or more attributes of one or more groups of blocks of oneor more threads. In at least one embodiment, parallel processing unit5200 is used to perform an application programming interface to indicatea maximum number of blocks of threads to be scheduled in parallel. In atleast one embodiment, parallel processing unit 5200 is used to performan application programming interface to cause a kernel to be generatedto cause two or more blocks of two or more threads to be scheduled inparallel. In at least one embodiment, parallel processing unit 5200 isused to perform an application programming interface comprising one ormore parameters to indicate one or more limitations of one or moreattributes of one or more groups of blocks of one or more threads. In atleast one embodiment, parallel processing unit 5200 is used to performan application programming interface to indicate whether one or morethreads within two or more blocks of threads have performed a barrierinstruction. In at least one embodiment, parallel processing unit 5200is used to perform an application programming interface to causeperformance of one or more threads within a group of blocks of threadsto stop at least until all threads within the group of blocks haveperformed a barrier instruction. In at least one embodiment, parallelprocessing unit 5200 is used to perform an application programminginterface to indicate whether one or more threads within two or moreblocks of threads have performed a barrier instruction and to causeperformance of one or more threads within the group of blocks of threadsto stop at least until all threads within the group of blocks haveperformed the barrier instruction. In at least one embodiment, parallelprocessing unit 5200 is used to perform an application programminginterface to cause memory to be shared between two or more groups ofblocks of threads.

In at least one embodiment, parallel processing unit 5200 is used toperform at least one aspect described with respect to example computersystem 100, example diagram 200, example diagram 300, example diagram400, example diagram 500, example process 600, example diagram 700,example application programming interface 800, example applicationprogramming interface 900, example diagram 1000, example diagram 1100,example application programming interface 1200, example applicationprogramming interface 1300, example computer system 1400, exampleapplication programming interface 1500, example diagram 1600, exampleapplication programming interface 1700, example computer system 1800,example application programming interface 1900, example computer system2000, example application programming interface 2100, example diagram2200, example diagram 2300, example diagram 2400, example diagram 2500,example application programming interface 2600, example diagram 2700,example diagram 2800, example diagram 2900, example applicationprogramming interface 3000, example application programming interface3100, example application programming interface 3200, example diagram3300, example application programming interface 3400, example softwarestack 3500, and/or other systems, methods, or operations describedherein.

FIG. 53 illustrates a GPC 5300, in accordance with at least oneembodiment. In at least one embodiment, GPC 5300 is GPC 5218 of FIG. 52. In at least one embodiment, each GPC 5300 includes, withoutlimitation, a number of hardware units for processing tasks and each GPC5300 includes, without limitation, a pipeline manager 5302, a pre-rasteroperations unit (“PROP”) 5304, a raster engine 5308, a work distributioncrossbar (“WDX”) 5316, an MMU 5318, one or more Data Processing Clusters(“DPCs”) 5306, and any suitable combination of parts.

In at least one embodiment, operation of GPC 5300 is controlled bypipeline manager 5302. In at least one embodiment, pipeline manager 5302manages configuration of one or more DPCs 5306 for processing tasksallocated to GPC 5300. In at least one embodiment, pipeline manager 5302configures at least one of one or more DPCs 5306 to implement at least aportion of a graphics rendering pipeline. In at least one embodiment,DPC 5306 is configured to execute a vertex shader program on aprogrammable streaming multiprocessor (“SM”) 5314. In at least oneembodiment, pipeline manager 5302 is configured to route packetsreceived from a work distribution unit to appropriate logical unitswithin GPC 5300 and, in at least one embodiment, some packets may berouted to fixed function hardware units in PROP 5304 and/or rasterengine 5308 while other packets may be routed to DPCs 5306 forprocessing by a primitive engine 5312 or SM 5314. In at least oneembodiment, pipeline manager 5302 configures at least one of DPCs 5306to implement a computing pipeline. In at least one embodiment, pipelinemanager 5302 configures at least one of DPCs 5306 to execute at least aportion of a CUDA program.

In at least one embodiment, PROP unit 5304 is configured to route datagenerated by raster engine 5308 and DPCs 5306 to a Raster Operations(“ROP”) unit in a partition unit, such as memory partition unit 5222described in more detail above in conjunction with FIG. 52 . In at leastone embodiment, PROP unit 5304 is configured to perform optimizationsfor color blending, organize pixel data, perform address translations,and more. In at least one embodiment, raster engine 5308 includes,without limitation, a number of fixed function hardware units configuredto perform various raster operations and, in at least one embodiment,raster engine 5308 includes, without limitation, a setup engine, acoarse raster engine, a culling engine, a clipping engine, a fine rasterengine, a tile coalescing engine, and any suitable combination thereof.In at least one embodiment, a setup engine receives transformed verticesand generates plane equations associated with geometric primitivedefined by vertices; plane equations are transmitted to a coarse rasterengine to generate coverage information (e.g., an x, y coverage mask fora tile) for a primitive; the output of the coarse raster engine istransmitted to a culling engine where fragments associated with aprimitive that fail a z-test are culled, and transmitted to a clippingengine where fragments lying outside a viewing frustum are clipped. Inat least one embodiment, fragments that survive clipping and culling arepassed to a fine raster engine to generate attributes for pixelfragments based on plane equations generated by a setup engine. In atleast one embodiment, the output of raster engine 5308 comprisesfragments to be processed by any suitable entity such as by a fragmentshader implemented within DPC 5306.

In at least one embodiment, each DPC 5306 included in GPC 5300 comprise,without limitation, an M-Pipe Controller (“MPC”) 5310; primitive engine5312; one or more SMs 5314; and any suitable combination thereof. In atleast one embodiment, MPC 5310 controls operation of DPC 5306, routingpackets received from pipeline manager 5302 to appropriate units in DPC5306. In at least one embodiment, packets associated with a vertex arerouted to primitive engine 5312, which is configured to fetch vertexattributes associated with vertex from memory; in contrast, packetsassociated with a shader program may be transmitted to SM 5314.

In at least one embodiment, SM 5314 comprises, without limitation, aprogrammable streaming processor that is configured to process tasksrepresented by a number of threads. In at least one embodiment, SM 5314is multi-threaded and configured to execute a plurality of threads(e.g., 32 threads) from a particular group of threads concurrently andimplements a SIMD architecture where each thread in a group of threads(e.g., a warp) is configured to process a different set of data based onsame set of instructions. In at least one embodiment, all threads ingroup of threads execute same instructions. In at least one embodiment,SM 5314 implements a SIMT architecture wherein each thread in a group ofthreads is configured to process a different set of data based on sameset of instructions, but where individual threads in group of threadsare allowed to diverge during execution. In at least one embodiment, aprogram counter, a call stack, and an execution state is maintained foreach warp, enabling concurrency between warps and serial executionwithin warps when threads within a warp diverge. In another embodiment,a program counter, a call stack, and an execution state is maintainedfor each individual thread, enabling equal concurrency between allthreads, within and between warps. In at least one embodiment, anexecution state is maintained for each individual thread and threadsexecuting the same instructions may be converged and executed inparallel for better efficiency. At least one embodiment of SM 5314 isdescribed in more detail in conjunction with FIG. 54 .

In at least one embodiment, MMU 5318 provides an interface between GPC5300 and a memory partition unit (e.g., partition unit 5222 of FIG. 52 )and MMU 5318 provides translation of virtual addresses into physicaladdresses, memory protection, and arbitration of memory requests. In atleast one embodiment, MMU 5318 provides one or more translationlookaside buffers (TLBs) for performing translation of virtual addressesinto physical addresses in memory.

In at least one embodiment, at least one component shown or describedwith respect to FIG. 53 is used to implement techniques and/or functionsdescribed in connection with FIGS. 1-35 . In at least one embodiment,general processing cluster 5300 is used to perform an applicationprogramming interface to indicate two or more blocks of threads to bescheduled in parallel. In at least one embodiment, general processingcluster 5300 is used to perform an application programming interface todetermine which of two or more blocks of threads to be scheduled inparallel. In at least one embodiment, general processing cluster 5300 isused to perform an application programming interface comprising one ormore parameters to cause a scheduling policy of one or more blocks ofone or more threads to be performed. In at least one embodiment, generalprocessing cluster 5300 is used to perform an application programminginterface comprising one or more parameters to indicate a schedulingpolicy of one or more blocks of one or more threads. In at least oneembodiment, general processing cluster 5300 is used to perform anapplication programming interface to indicate a maximum number of blocksof threads capable of being scheduled in parallel. In at least oneembodiment, general processing cluster 5300 is used to perform anapplication programming interface comprising one or more parameters toindicate one or more attributes of one or more groups of blocks of oneor more threads. In at least one embodiment, general processing cluster5300 is used to perform an application programming interface to indicatea maximum number of blocks of threads to be scheduled in parallel. In atleast one embodiment, general processing cluster 5300 is used to performan application programming interface to cause a kernel to be generatedto cause two or more blocks of two or more threads to be scheduled inparallel. In at least one embodiment, general processing cluster 5300 isused to perform an application programming interface comprising one ormore parameters to indicate one or more limitations of one or moreattributes of one or more groups of blocks of one or more threads. In atleast one embodiment, general processing cluster 5300 is used to performan application programming interface to indicate whether one or morethreads within two or more blocks of threads have performed a barrierinstruction. In at least one embodiment, general processing cluster 5300is used to perform an application programming interface to causeperformance of one or more threads within a group of blocks of threadsto stop at least until all threads within the group of blocks haveperformed a barrier instruction. In at least one embodiment, generalprocessing cluster 5300 is used to perform an application programminginterface to indicate whether one or more threads within two or moreblocks of threads have performed a barrier instruction and to causeperformance of one or more threads within the group of blocks of threadsto stop at least until all threads within the group of blocks haveperformed the barrier instruction. In at least one embodiment, generalprocessing cluster 5300 is used to perform an application programminginterface to cause memory to be shared between two or more groups ofblocks of threads.

In at least one embodiment, general processing cluster 5300 is used toperform at least one aspect described with respect to example computersystem 100, example diagram 200, example diagram 300, example diagram400, example diagram 500, example process 600, example diagram 700,example application programming interface 800, example applicationprogramming interface 900, example diagram 1000, example diagram 1100,example application programming interface 1200, example applicationprogramming interface 1300, example computer system 1400, exampleapplication programming interface 1500, example diagram 1600, exampleapplication programming interface 1700, example computer system 1800,example application programming interface 1900, example computer system2000, example application programming interface 2100, example diagram2200, example diagram 2300, example diagram 2400, example diagram 2500,example application programming interface 2600, example diagram 2700,example diagram 2800, example diagram 2900, example applicationprogramming interface 3000, example application programming interface3100, example application programming interface 3200, example diagram3300, example application programming interface 3400, example softwarestack 3500, and/or other systems, methods, or operations describedherein.

FIG. 54 illustrates a streaming multiprocessor (“SM”) 5400, inaccordance with at least one embodiment. In at least one embodiment, SM5400 is SM 5314 of FIG. 53 . In at least one embodiment, SM 5400includes, without limitation, an instruction cache 5402; one or morescheduler units 5404; a register file 5408; one or more processing cores(“cores”) 5410; one or more special function units (“SFUs”) 5412; one ormore LSUs 5414; an interconnect network 5416; a shared memory/L1 cache5418; and any suitable combination thereof. In at least one embodiment,a work distribution unit dispatches tasks for execution on GPCs ofparallel processing units (PPUs) and each task is allocated to aparticular Data Processing Cluster (DPC) within a GPC and, if a task isassociated with a shader program, then the task is allocated to one ofSMs 5400. In at least one embodiment, scheduler unit 5404 receives tasksfrom a work distribution unit and manages instruction scheduling for oneor more thread blocks assigned to SM 5400. In at least one embodiment,scheduler unit 5404 schedules thread blocks for execution as warps ofparallel threads, wherein each thread block is allocated at least onewarp. In at least one embodiment, each warp executes threads. In atleast one embodiment, scheduler unit 5404 manages a plurality ofdifferent thread blocks, allocating warps to different thread blocks andthen dispatching instructions from a plurality of different cooperativegroups to various functional units (e.g., processing cores 5410, SFUs5412, and LSUs 5414) during each clock cycle.

In at least one embodiment, “cooperative groups” may refer to aprogramming model for organizing groups of communicating threads thatallows developers to express granularity at which threads arecommunicating, enabling expression of richer, more efficient paralleldecompositions. In at least one embodiment, cooperative launch APIssupport synchronization amongst thread blocks for execution of parallelalgorithms. In at least one embodiment, APIs of conventional programmingmodels provide a single, simple construct for synchronizing cooperatingthreads: a barrier across all threads of a thread block (e.g.,syncthreads( ) function). However, in at least one embodiment,programmers may define groups of threads at smaller than thread blockgranularities and synchronize within defined groups to enable greaterperformance, design flexibility, and software reuse in the form ofcollective group-wide function interfaces. In at least one embodiment,cooperative groups enable programmers to define groups of threadsexplicitly at sub-block and multi-block granularities, and to performcollective operations such as synchronization on threads in acooperative group. In at least one embodiment, a sub-block granularityis as small as a single thread. In at least one embodiment, aprogramming model supports clean composition across software boundaries,so that libraries and utility functions can synchronize safely withintheir local context without having to make assumptions aboutconvergence. In at least one embodiment, cooperative group primitivesenable new patterns of cooperative parallelism, including, withoutlimitation, producer-consumer parallelism, opportunistic parallelism,and global synchronization across an entire grid of thread blocks.

In at least one embodiment, a dispatch unit 5406 is configured totransmit instructions to one or more of functional units and schedulerunit 5404 includes, without limitation, two dispatch units 5406 thatenable two different instructions from same warp to be dispatched duringeach clock cycle. In at least one embodiment, each scheduler unit 5404includes a single dispatch unit 5406 or additional dispatch units 5406.

In at least one embodiment, each SM 5400, in at least one embodiment,includes, without limitation, register file 5408 that provides a set ofregisters for functional units of SM 5400. In at least one embodiment,register file 5408 is divided between each of the functional units suchthat each functional unit is allocated a dedicated portion of registerfile 5408. In at least one embodiment, register file 5408 is dividedbetween different warps being executed by SM 5400 and register file 5408provides temporary storage for operands connected to data paths offunctional units. In at least one embodiment, each SM 5400 comprises,without limitation, a plurality of L processing cores 5410. In at leastone embodiment, SM 5400 includes, without limitation, a large number(e.g., 128 or more) of distinct processing cores 5410. In at least oneembodiment, each processing core 5410 includes, without limitation, afully-pipelined, single-precision, double-precision, and/or mixedprecision processing unit that includes, without limitation, a floatingpoint arithmetic logic unit and an integer arithmetic logic unit. In atleast one embodiment, floating point arithmetic logic units implementIEEE 754-2008 standard for floating point arithmetic. In at least oneembodiment, processing cores 5410 include, without limitation, 64single-precision (32-bit) floating point cores, 64 integer cores, 32double-precision (64-bit) floating point cores, and 8 tensor cores.

In at least one embodiment, tensor cores are configured to performmatrix operations. In at least one embodiment, one or more tensor coresare included in processing cores 5410. In at least one embodiment,tensor cores are configured to perform deep learning matrix arithmetic,such as convolution operations for neural network training andinferencing. In at least one embodiment, each tensor core operates on a4×4 matrix and performs a matrix multiply and accumulate operationD=A×B+C, where A, B, C, and D are 4×4 matrices.

In at least one embodiment, matrix multiply inputs A and B are 16-bitfloating point matrices and accumulation matrices C and D are 16-bitfloating point or 32-bit floating point matrices. In at least oneembodiment, tensor cores operate on 16-bit floating point input datawith 32-bit floating point accumulation. In at least one embodiment,16-bit floating point multiply uses 64 operations and results in a fullprecision product that is then accumulated using 32-bit floating pointaddition with other intermediate products for a 4×4×4 matrix multiply.Tensor cores are used to perform much larger two-dimensional or higherdimensional matrix operations, built up from these smaller elements, inat least one embodiment. In at least one embodiment, an API, such as aCUDA-C++ API, exposes specialized matrix load, matrix multiply andaccumulate, and matrix store operations to efficiently use tensor coresfrom a CUDA-C++ program. In at least one embodiment, at the CUDA level,a warp-level interface assumes 16×16 size matrices spanning all 32threads of a warp.

In at least one embodiment, each SM 5400 comprises, without limitation,M SFUs 5412 that perform special functions (e.g., attribute evaluation,reciprocal square root, and like). In at least one embodiment, SFUs 5412include, without limitation, a tree traversal unit configured totraverse a hierarchical tree data structure. In at least one embodiment,SFUs 5412 include, without limitation, a texture unit configured toperform texture map filtering operations. In at least one embodiment,texture units are configured to load texture maps (e.g., a 2D array oftexels) from memory and sample texture maps to produce sampled texturevalues for use in shader programs executed by SM 5400. In at least oneembodiment, texture maps are stored in shared memory/L1 cache 5418. Inat least one embodiment, texture units implement texture operations suchas filtering operations using mip-maps (e.g., texture maps of varyinglevels of detail). In at least one embodiment, each SM 5400 includes,without limitation, two texture units.

In at least one embodiment, each SM 5400 comprises, without limitation,N LSUs 5414 that implement load and store operations between sharedmemory/L1 cache 5418 and register file 5408. In at least one embodiment,each SM 5400 includes, without limitation, interconnect network 5416that connects each of the functional units to register file 5408 and LSU5414 to register file 5408 and shared memory/L1 cache 5418. In at leastone embodiment, interconnect network 5416 is a crossbar that can beconfigured to connect any of the functional units to any of theregisters in register file 5408 and connect LSUs 5414 to register file5408 and memory locations in shared memory/L1 cache 5418.

In at least one embodiment, shared memory/L1 cache 5418 is an array ofon-chip memory that allows for data storage and communication between SM5400 and a primitive engine and between threads in SM 5400. In at leastone embodiment, shared memory/L1 cache 5418 comprises, withoutlimitation, 128 KB of storage capacity and is in a path from SM 5400 toa partition unit. In at least one embodiment, shared memory/L1 cache5418 is used to cache reads and writes. In at least one embodiment, oneor more of shared memory/L1 cache 5418, L2 cache, and memory are backingstores.

In at least one embodiment, combining data cache and shared memoryfunctionality into a single memory block provides improved performancefor both types of memory accesses. In at least one embodiment, capacityis used or is usable as a cache by programs that do not use sharedmemory, such as if shared memory is configured to use half of capacity,texture and load/store operations can use remaining capacity. In atleast one embodiment, integration within shared memory/L1 cache 5418enables shared memory/L1 cache 5418 to function as a high-throughputconduit for streaming data while simultaneously providing high-bandwidthand low-latency access to frequently reused data. In at least oneembodiment, when configured for general purpose parallel computation, asimpler configuration can be used compared with graphics processing. Inat least one embodiment, fixed function GPUs are bypassed, creating amuch simpler programming model. In at least one embodiment and in ageneral purpose parallel computation configuration, a work distributionunit assigns and distributes blocks of threads directly to DPCs. In atleast one embodiment, threads in a block execute the same program, usinga unique thread ID in a calculation to ensure each thread generatesunique results, using SM 5400 to execute a program and performcalculations, shared memory/L1 cache 5418 to communicate betweenthreads, and LSU 5414 to read and write global memory through sharedmemory/L1 cache 5418 and a memory partition unit. In at least oneembodiment, when configured for general purpose parallel computation, SM5400 writes commands that scheduler unit 5404 can use to launch new workon DPCs.

In at least one embodiment, PPU is included in or coupled to a desktopcomputer, a laptop computer, a tablet computer, servers, supercomputers,a smart-phone (e.g., a wireless, hand-held device), a PDA, a digitalcamera, a vehicle, a head mounted display, a hand-held electronicdevice, and more. In at least one embodiment, PPU is embodied on asingle semiconductor substrate. In at least one embodiment, PPU isincluded in an SoC along with one or more other devices such asadditional PPUs, memory, a RISC CPU, an MMU, a digital-to-analogconverter (“DAC”), and like.

In at least one embodiment, PPU may be included on a graphics card thatincludes one or more memory devices. In at least one embodiment, agraphics card may be configured to interface with a PCIe slot on amotherboard of a desktop computer. In at least one embodiment, PPU maybe an integrated GPU (“iGPU”) included in chipset of motherboard.

In at least one embodiment, at least one component shown or describedwith respect to FIG. 54 is used to implement techniques and/or functionsdescribed in connection with FIGS. 1-35 . In at least one embodiment,streaming multiprocessor 5400 is used to perform an applicationprogramming interface to indicate two or more blocks of threads to bescheduled in parallel. In at least one embodiment, streamingmultiprocessor 5400 is used to perform an application programminginterface to determine which of two or more blocks of threads to bescheduled in parallel. In at least one embodiment, streamingmultiprocessor 5400 is used to perform an application programminginterface comprising one or more parameters to cause a scheduling policyof one or more blocks of one or more threads to be performed. In atleast one embodiment, streaming multiprocessor 5400 is used to performan application programming interface comprising one or more parametersto indicate a scheduling policy of one or more blocks of one or morethreads. In at least one embodiment, streaming multiprocessor 5400 isused to perform an application programming interface to indicate amaximum number of blocks of threads capable of being scheduled inparallel. In at least one embodiment, streaming multiprocessor 5400 isused to perform an application programming interface comprising one ormore parameters to indicate one or more attributes of one or more groupsof blocks of one or more threads. In at least one embodiment, streamingmultiprocessor 5400 is used to perform an application programminginterface to indicate a maximum number of blocks of threads to bescheduled in parallel. In at least one embodiment, streamingmultiprocessor 5400 is used to perform an application programminginterface to cause a kernel to be generated to cause two or more blocksof two or more threads to be scheduled in parallel. In at least oneembodiment, streaming multiprocessor 5400 is used to perform anapplication programming interface comprising one or more parameters toindicate one or more limitations of one or more attributes of one ormore groups of blocks of one or more threads. In at least oneembodiment, streaming multiprocessor 5400 is used to perform anapplication programming interface to indicate whether one or morethreads within two or more blocks of threads have performed a barrierinstruction. In at least one embodiment, streaming multiprocessor 5400is used to perform an application programming interface to causeperformance of one or more threads within a group of blocks of threadsto stop at least until all threads within the group of blocks haveperformed a barrier instruction. In at least one embodiment, streamingmultiprocessor 5400 is used to perform an application programminginterface to indicate whether one or more threads within two or moreblocks of threads have performed a barrier instruction and to causeperformance of one or more threads within the group of blocks of threadsto stop at least until all threads within the group of blocks haveperformed the barrier instruction. In at least one embodiment, streamingmultiprocessor 5400 is used to perform an application programminginterface to cause memory to be shared between two or more groups ofblocks of threads.

In at least one embodiment, streaming multiprocessor 5400 is used toperform at least one aspect described with respect to example computersystem 100, example diagram 200, example diagram 300, example diagram400, example diagram 500, example process 600, example diagram 700,example application programming interface 800, example applicationprogramming interface 900, example diagram 1000, example diagram 1100,example application programming interface 1200, example applicationprogramming interface 1300, example computer system 1400, exampleapplication programming interface 1500, example diagram 1600, exampleapplication programming interface 1700, example computer system 1800,example application programming interface 1900, example computer system2000, example application programming interface 2100, example diagram2200, example diagram 2300, example diagram 2400, example diagram 2500,example application programming interface 2600, example diagram 2700,example diagram 2800, example diagram 2900, example applicationprogramming interface 3000, example application programming interface3100, example application programming interface 3200, example diagram3300, example application programming interface 3400, example softwarestack 3500, and/or other systems, methods, or operations describedherein.

Software Constructions for General-Purpose Computing

The following figures set forth, without limitation, exemplary softwareconstructs for implementing at least one embodiment.

FIG. 55 illustrates a software stack of a programming platform, inaccordance with at least one embodiment. In at least one embodiment, aprogramming platform is a platform for leveraging hardware on acomputing system to accelerate computational tasks. A programmingplatform may be accessible to software developers through libraries,compiler directives, and/or extensions to programming languages, in atleast one embodiment. In at least one embodiment, a programming platformmay be, but is not limited to, CUDA, Radeon Open Compute Platform(“ROCm”), OpenCL (OpenCL™ is developed by Khronos group), SYCL, or IntelOne API.

In at least one embodiment, a software stack 5500 of a programmingplatform provides an execution environment for an application 5501. Inat least one embodiment, application 5501 may include any computersoftware capable of being launched on software stack 5500. In at leastone embodiment, application 5501 may include, but is not limited to, anartificial intelligence (“AI”)/machine learning (“ML”) application, ahigh performance computing (“HPC”) application, a virtual desktopinfrastructure (“VDI”), or a data center workload.

In at least one embodiment, application 5501 and software stack 5500 runon hardware 5507. Hardware 5507 may include one or more GPUs, CPUs,FPGAs, AI engines, and/or other types of compute devices that support aprogramming platform, in at least one embodiment. In at least oneembodiment, such as with CUDA, software stack 5500 may be vendorspecific and compatible with only devices from particular vendor(s). Inat least one embodiment, such as in with OpenCL, software stack 5500 maybe used with devices from different vendors. In at least one embodiment,hardware 5507 includes a host connected to one more devices that can beaccessed to perform computational tasks via application programminginterface (“API”) calls. A device within hardware 5507 may include, butis not limited to, a GPU, FPGA, AI engine, or other compute device (butmay also include a CPU) and its memory, as opposed to a host withinhardware 5507 that may include, but is not limited to, a CPU (but mayalso include a compute device) and its memory, in at least oneembodiment.

In at least one embodiment, software stack 5500 of a programmingplatform includes, without limitation, a number of libraries 5503, aruntime 5505, and a device kernel driver 5506. Each of libraries 5503may include data and programming code that can be used by computerprograms and leveraged during software development, in at least oneembodiment. In at least one embodiment, libraries 5503 may include, butare not limited to, pre-written code and subroutines, classes, values,type specifications, configuration data, documentation, help data,and/or message templates. In at least one embodiment, libraries 5503include functions that are optimized for execution on one or more typesof devices. In at least one embodiment, libraries 5503 may include, butare not limited to, functions for performing mathematical, deeplearning, and/or other types of operations on devices. In at least oneembodiment, libraries 5503 are associated with corresponding APIs 5502,which may include one or more APIs, that expose functions implemented inlibraries 5503.

In at least one embodiment, application 5501 is written as source codethat is compiled into executable code, as discussed in greater detailbelow in conjunction with FIGS. 60-62 . Executable code of application5501 may run, at least in part, on an execution environment provided bysoftware stack 5500, in at least one embodiment. In at least oneembodiment, during execution of application 5501, code may be reachedthat needs to run on a device, as opposed to a host. In such a case,runtime 5505 may be called to load and launch requisite code on thedevice, in at least one embodiment. In at least one embodiment, runtime5505 may include any technically feasible runtime system that is able tosupport execution of application S01.

In at least one embodiment, runtime 5505 is implemented as one or moreruntime libraries associated with corresponding APIs, which are shown asAPI(s) 5504. One or more of such runtime libraries may include, withoutlimitation, functions for memory management, execution control, devicemanagement, error handling, and/or synchronization, among other things,in at least one embodiment. In at least one embodiment, memorymanagement functions may include, but are not limited to, functions toallocate, deallocate, and copy device memory, as well as transfer databetween host memory and device memory. In at least one embodiment,execution control functions may include, but are not limited to,functions to launch a function (sometimes referred to as a “kernel” whena function is a global function callable from a host) on a device andset attribute values in a buffer maintained by a runtime library for agiven function to be executed on a device.

Runtime libraries and corresponding API(s) 5504 may be implemented inany technically feasible manner, in at least one embodiment. In at leastone embodiment, one (or any number of) API may expose a low-level set offunctions for fine-grained control of a device, while another (or anynumber of) API may expose a higher-level set of such functions. In atleast one embodiment, a high-level runtime API may be built on top of alow-level API. In at least one embodiment, one or more of runtime APIsmay be language-specific APIs that are layered on top of alanguage-independent runtime API.

In at least one embodiment, device kernel driver 5506 is configured tofacilitate communication with an underlying device. In at least oneembodiment, device kernel driver 5506 may provide low-levelfunctionalities upon which APIs, such as API(s) 5504, and/or othersoftware relies. In at least one embodiment, device kernel driver 5506may be configured to compile intermediate representation (“IR”) codeinto binary code at runtime. For CUDA, device kernel driver 5506 maycompile Parallel Thread Execution (“PTX”) IR code that is not hardwarespecific into binary code for a specific target device at runtime (withcaching of compiled binary code), which is also sometimes referred to as“finalizing” code, in at least one embodiment. Doing so may permitfinalized code to run on a target device, which may not have existedwhen source code was originally compiled into PTX code, in at least oneembodiment. Alternatively, in at least one embodiment, device sourcecode may be compiled into binary code offline, without requiring devicekernel driver 5506 to compile IR code at runtime.

In at least one embodiment, at least one component shown or describedwith respect to FIG. 55 is used to implement techniques and/or functionsdescribed in connection with FIGS. 1-35 . In at least one embodiment, atleast one element of software stack 5500 of a programming platform isused to perform an application programming interface to indicate two ormore blocks of threads to be scheduled in parallel. In at least oneembodiment, at least one element of software stack 5500 of a programmingplatform is used to perform an application programming interface todetermine which of two or more blocks of threads to be scheduled inparallel. In at least one embodiment, at least one element of softwarestack 5500 of a programming platform is used to perform an applicationprogramming interface comprising one or more parameters to cause ascheduling policy of one or more blocks of one or more threads to beperformed. In at least one embodiment, at least one element of softwarestack 5500 of a programming platform is used to perform an applicationprogramming interface comprising one or more parameters to indicate ascheduling policy of one or more blocks of one or more threads. In atleast one embodiment, at least one element of software stack 5500 of aprogramming platform is used to perform an application programminginterface to indicate a maximum number of blocks of threads capable ofbeing scheduled in parallel. In at least one embodiment, at least oneelement of software stack 5500 of a programming platform is used toperform an application programming interface comprising one or moreparameters to indicate one or more attributes of one or more groups ofblocks of one or more threads. In at least one embodiment, at least oneelement of software stack 5500 of a programming platform is used toperform an application programming interface to indicate a maximumnumber of blocks of threads to be scheduled in parallel. In at least oneembodiment, at least one element of software stack 5500 of a programmingplatform is used to perform an application programming interface tocause a kernel to be generated to cause two or more blocks of two ormore threads to be scheduled in parallel. In at least one embodiment, atleast one element of software stack 5500 of a programming platform isused to perform an application programming interface comprising one ormore parameters to indicate one or more limitations of one or moreattributes of one or more groups of blocks of one or more threads. In atleast one embodiment, at least one element of software stack 5500 of aprogramming platform is used to perform an application programminginterface to indicate whether one or more threads within two or moreblocks of threads have performed a barrier instruction. In at least oneembodiment, at least one element of software stack 5500 of a programmingplatform is used to perform an application programming interface tocause performance of one or more threads within a group of blocks ofthreads to stop at least until all threads within the group of blockshave performed a barrier instruction. In at least one embodiment, atleast one element of software stack 5500 of a programming platform isused to perform an application programming interface to indicate whetherone or more threads within two or more blocks of threads have performeda barrier instruction and to cause performance of one or more threadswithin the group of blocks of threads to stop at least until all threadswithin the group of blocks have performed the barrier instruction. In atleast one embodiment, at least one element of software stack 5500 of aprogramming platform is used to perform an application programminginterface to cause memory to be shared between two or more groups ofblocks of threads.

In at least one embodiment, at least one element of software stack 5500of a programming platform is used to perform at least one aspectdescribed with respect to example computer system 100, example diagram200, example diagram 300, example diagram 400, example diagram 500,example process 600, example diagram 700, example applicationprogramming interface 800, example application programming interface900, example diagram 1000, example diagram 1100, example applicationprogramming interface 1200, example application programming interface1300, example computer system 1400, example application programminginterface 1500, example diagram 1600, example application programminginterface 1700, example computer system 1800, example applicationprogramming interface 1900, example computer system 2000, exampleapplication programming interface 2100, example diagram 2200, examplediagram 2300, example diagram 2400, example diagram 2500, exampleapplication programming interface 2600, example diagram 2700, examplediagram 2800, example diagram 2900, example application programminginterface 3000, example application programming interface 3100, exampleapplication programming interface 3200, example diagram 3300, exampleapplication programming interface 3400, example software stack 3500,and/or other systems, methods, or operations described herein.

FIG. 56 illustrates a CUDA implementation of software stack 5500 of FIG.55 , in accordance with at least one embodiment. In at least oneembodiment, a CUDA software stack 5600, on which an application 5601 maybe launched, includes CUDA libraries 5603, a CUDA runtime 5605, a CUDAdriver 5607, and a device kernel driver 5608. In at least oneembodiment, CUDA software stack 5600 executes on hardware 5609, whichmay include a GPU that supports CUDA and is developed by NVIDIACorporation of Santa Clara, CA.

In at least one embodiment, application 5601, CUDA runtime 5605, anddevice kernel driver 5608 may perform similar functionalities asapplication 5501, runtime 5505, and device kernel driver 5506,respectively, which are described above in conjunction with FIG. 55 . Inat least one embodiment, CUDA driver 5607 includes a library(libcuda.so) that implements a CUDA driver API 5606. Similar to a CUDAruntime API 5604 implemented by a CUDA runtime library (cudart), CUDAdriver API 5606 may, without limitation, expose functions for memorymanagement, execution control, device management, error handling,synchronization, and/or graphics interoperability, among other things,in at least one embodiment. In at least one embodiment, CUDA driver API5606 differs from CUDA runtime API 5604 in that CUDA runtime API 5604simplifies device code management by providing implicit initialization,context (analogous to a process) management, and module (analogous todynamically loaded libraries) management. In contrast to high-level CUDAruntime API 5604, CUDA driver API 5606 is a low-level API providing morefine-grained control of the device, particularly with respect tocontexts and module loading, in at least one embodiment. In at least oneembodiment, CUDA driver API 5606 may expose functions for contextmanagement that are not exposed by CUDA runtime API 5604. In at leastone embodiment, CUDA driver API 5606 is also language-independent andsupports, e.g., OpenCL in addition to CUDA runtime API 5604. Further, inat least one embodiment, development libraries, including CUDA runtime5605, may be considered as separate from driver components, includinguser-mode CUDA driver 5607 and kernel-mode device driver 5608 (alsosometimes referred to as a “display” driver).

In at least one embodiment, CUDA libraries 5603 may include, but are notlimited to, mathematical libraries, deep learning libraries, parallelalgorithm libraries, and/or signal/image/video processing libraries,which parallel computing applications such as application 5601 mayutilize. In at least one embodiment, CUDA libraries 5603 may includemathematical libraries such as a cuBLAS library that is animplementation of Basic Linear Algebra Subprograms (“BLAS”) forperforming linear algebra operations, a cuFFT library for computing fastFourier transforms (“FFTs”), and a cuRAND library for generating randomnumbers, among others. In at least one embodiment, CUDA libraries 5603may include deep learning libraries such as a cuDNN library ofprimitives for deep neural networks and a TensorRT platform forhigh-performance deep learning inference, among others.

In at least one embodiment, at least one component shown or describedwith respect to FIG. 56 is used to implement techniques and/or functionsdescribed in connection with FIGS. 1-35 . In at least one embodiment, atleast one element of CUDA software stack 5600 is used to perform anapplication programming interface to indicate two or more blocks ofthreads to be scheduled in parallel. In at least one embodiment, atleast one element of CUDA software stack 5600 is used to perform anapplication programming interface to determine which of two or moreblocks of threads to be scheduled in parallel. In at least oneembodiment, at least one element of CUDA software stack 5600 is used toperform an application programming interface comprising one or moreparameters to cause a scheduling policy of one or more blocks of one ormore threads to be performed. In at least one embodiment, at least oneelement of CUDA software stack 5600 is used to perform an applicationprogramming interface comprising one or more parameters to indicate ascheduling policy of one or more blocks of one or more threads. In atleast one embodiment, at least one element of CUDA software stack 5600is used to perform an application programming interface to indicate amaximum number of blocks of threads capable of being scheduled inparallel. In at least one embodiment, at least one element of CUDAsoftware stack 5600 is used to perform an application programminginterface comprising one or more parameters to indicate one or moreattributes of one or more groups of blocks of one or more threads. In atleast one embodiment, at least one element of CUDA software stack 5600is used to perform an application programming interface to indicate amaximum number of blocks of threads to be scheduled in parallel. In atleast one embodiment, at least one element of CUDA software stack 5600is used to perform an application programming interface to cause akernel to be generated to cause two or more blocks of two or morethreads to be scheduled in parallel. In at least one embodiment, atleast one element of CUDA software stack 5600 is used to perform anapplication programming interface comprising one or more parameters toindicate one or more limitations of one or more attributes of one ormore groups of blocks of one or more threads. In at least oneembodiment, at least one element of CUDA software stack 5600 is used toperform an application programming interface to indicate whether one ormore threads within two or more blocks of threads have performed abarrier instruction. In at least one embodiment, at least one element ofCUDA software stack 5600 is used to perform an application programminginterface to cause performance of one or more threads within a group ofblocks of threads to stop at least until all threads within the group ofblocks have performed a barrier instruction. In at least one embodiment,at least one element of CUDA software stack 5600 is used to perform anapplication programming interface to indicate whether one or morethreads within two or more blocks of threads have performed a barrierinstruction and to cause performance of one or more threads within thegroup of blocks of threads to stop at least until all threads within thegroup of blocks have performed the barrier instruction. In at least oneembodiment, at least one element of CUDA software stack 5600 is used toperform an application programming interface to cause memory to beshared between two or more groups of blocks of threads.

In at least one embodiment, at least one element of CUDA software stack5600 is used to perform at least one aspect described with respect toexample computer system 100, example diagram 200, example diagram 300,example diagram 400, example diagram 500, example process 600, examplediagram 700, example application programming interface 800, exampleapplication programming interface 900, example diagram 1000, examplediagram 1100, example application programming interface 1200, exampleapplication programming interface 1300, example computer system 1400,example application programming interface 1500, example diagram 1600,example application programming interface 1700, example computer system1800, example application programming interface 1900, example computersystem 2000, example application programming interface 2100, examplediagram 2200, example diagram 2300, example diagram 2400, examplediagram 2500, example application programming interface 2600, examplediagram 2700, example diagram 2800, example diagram 2900, exampleapplication programming interface 3000, example application programminginterface 3100, example application programming interface 3200, examplediagram 3300, example application programming interface 3400, examplesoftware stack 3500, and/or other systems, methods, or operationsdescribed herein.

FIG. 57 illustrates a ROCm implementation of software stack 5500 of FIG.55 , in accordance with at least one embodiment. In at least oneembodiment, a ROCm software stack 5700, on which an application 5701 maybe launched, includes a language runtime 5703, a system runtime 5705, athunk 5707, and a ROCm kernel driver 5708. In at least one embodiment,ROCm software stack 5700 executes on hardware 5709, which may include aGPU that supports ROCm and is developed by AMD Corporation of SantaClara, CA.

In at least one embodiment, application 5701 may perform similarfunctionalities as application 5501 discussed above in conjunction withFIG. 55 . In addition, language runtime 5703 and system runtime 5705 mayperform similar functionalities as runtime 5505 discussed above inconjunction with FIG. 55 , in at least one embodiment. In at least oneembodiment, language runtime 5703 and system runtime 5705 differ in thatsystem runtime 5705 is a language-independent runtime that implements aROCr system runtime API 5704 and makes use of a Heterogeneous SystemArchitecture (“HSA”) Runtime API. HSA runtime API is a thin, user-modeAPI that exposes interfaces to access and interact with an AMD GPU,including functions for memory management, execution control viaarchitected dispatch of kernels, error handling, system and agentinformation, and runtime initialization and shutdown, among otherthings, in at least one embodiment. In contrast to system runtime 5705,language runtime 5703 is an implementation of a language-specificruntime API 5702 layered on top of ROCr system runtime API 5704, in atleast one embodiment. In at least one embodiment, language runtime APImay include, but is not limited to, a Heterogeneous compute Interfacefor Portability (“HIP”) language runtime API, a Heterogeneous ComputeCompiler (“HCC”) language runtime API, or an OpenCL API, among others.HIP language in particular is an extension of C++ programming languagewith functionally similar versions of CUDA mechanisms, and, in at leastone embodiment, a HIP language runtime API includes functions that aresimilar to those of CUDA runtime API 5604 discussed above in conjunctionwith FIG. 56 , such as functions for memory management, executioncontrol, device management, error handling, and synchronization, amongother things.

In at least one embodiment, thunk (ROCt) 5707 is an interface 5706 thatcan be used to interact with underlying ROCm driver 5708. In at leastone embodiment, ROCm driver 5708 is a ROCk driver, which is acombination of an AMDGPU driver and a HSA kernel driver (amdkfd). In atleast one embodiment, AMDGPU driver is a device kernel driver for GPUsdeveloped by AMD that performs similar functionalities as device kerneldriver 5506 discussed above in conjunction with FIG. 55 . In at leastone embodiment, HSA kernel driver is a driver permitting different typesof processors to share system resources more effectively via hardwarefeatures.

In at least one embodiment, various libraries (not shown) may beincluded in ROCm software stack 5700 above language runtime 5703 andprovide functionality similarity to CUDA libraries 5603, discussed abovein conjunction with FIG. 56 . In at least one embodiment, variouslibraries may include, but are not limited to, mathematical, deeplearning, and/or other libraries such as a hipBLAS library thatimplements functions similar to those of CUDA cuBLAS, a rocFFT libraryfor computing FFTs that is similar to CUDA cuFFT, among others.

In at least one embodiment, at least one component shown or describedwith respect to FIG. 57 is used to implement techniques and/or functionsdescribed in connection with FIGS. 1-35 . In at least one embodiment, atleast one element of ROCm software stack 5700 is used to perform anapplication programming interface to indicate two or more blocks ofthreads to be scheduled in parallel. In at least one embodiment, atleast one element of ROCm software stack 5700 is used to perform anapplication programming interface to determine which of two or moreblocks of threads to be scheduled in parallel. In at least oneembodiment, at least one element of ROCm software stack 5700 is used toperform an application programming interface comprising one or moreparameters to cause a scheduling policy of one or more blocks of one ormore threads to be performed. In at least one embodiment, at least oneelement of ROCm software stack 5700 is used to perform an applicationprogramming interface comprising one or more parameters to indicate ascheduling policy of one or more blocks of one or more threads. In atleast one embodiment, at least one element of ROCm software stack 5700is used to perform an application programming interface to indicate amaximum number of blocks of threads capable of being scheduled inparallel. In at least one embodiment, at least one element of ROCmsoftware stack 5700 is used to perform an application programminginterface comprising one or more parameters to indicate one or moreattributes of one or more groups of blocks of one or more threads. In atleast one embodiment, at least one element of ROCm software stack 5700is used to perform an application programming interface to indicate amaximum number of blocks of threads to be scheduled in parallel. In atleast one embodiment, at least one element of ROCm software stack 5700is used to perform an application programming interface to cause akernel to be generated to cause two or more blocks of two or morethreads to be scheduled in parallel. In at least one embodiment, atleast one element of ROCm software stack 5700 is used to perform anapplication programming interface comprising one or more parameters toindicate one or more limitations of one or more attributes of one ormore groups of blocks of one or more threads. In at least oneembodiment, at least one element of ROCm software stack 5700 is used toperform an application programming interface to indicate whether one ormore threads within two or more blocks of threads have performed abarrier instruction. In at least one embodiment, at least one element ofROCm software stack 5700 is used to perform an application programminginterface to cause performance of one or more threads within a group ofblocks of threads to stop at least until all threads within the group ofblocks have performed a barrier instruction. In at least one embodiment,at least one element of ROCm software stack 5700 is used to perform anapplication programming interface to indicate whether one or morethreads within two or more blocks of threads have performed a barrierinstruction and to cause performance of one or more threads within thegroup of blocks of threads to stop at least until all threads within thegroup of blocks have performed the barrier instruction. In at least oneembodiment, at least one element of ROCm software stack 5700 is used toperform an application programming interface to cause memory to beshared between two or more groups of blocks of threads.

In at least one embodiment, at least one element of ROCm software stack5700 is used to perform at least one aspect described with respect toexample computer system 100, example diagram 200, example diagram 300,example diagram 400, example diagram 500, example process 600, examplediagram 700, example application programming interface 800, exampleapplication programming interface 900, example diagram 1000, examplediagram 1100, example application programming interface 1200, exampleapplication programming interface 1300, example computer system 1400,example application programming interface 1500, example diagram 1600,example application programming interface 1700, example computer system1800, example application programming interface 1900, example computersystem 2000, example application programming interface 2100, examplediagram 2200, example diagram 2300, example diagram 2400, examplediagram 2500, example application programming interface 2600, examplediagram 2700, example diagram 2800, example diagram 2900, exampleapplication programming interface 3000, example application programminginterface 3100, example application programming interface 3200, examplediagram 3300, example application programming interface 3400, examplesoftware stack 3500, and/or other systems, methods, or operationsdescribed herein.

FIG. 58 illustrates an OpenCL implementation of software stack 5500 ofFIG. 55 , in accordance with at least one embodiment. In at least oneembodiment, an OpenCL software stack 5800, on which an application 5801may be launched, includes an OpenCL framework 5810, an OpenCL runtime5806, and a driver 5807. In at least one embodiment, OpenCL softwarestack 5800 executes on hardware 5609 that is not vendor-specific. AsOpenCL is supported by devices developed by different vendors, specificOpenCL drivers may be required to interoperate with hardware from suchvendors, in at least one embodiment.

In at least one embodiment, application 5801, OpenCL runtime 5806,device kernel driver 5807, and hardware 5808 may perform similarfunctionalities as application 5501, runtime 5505, device kernel driver5506, and hardware 5507, respectively, that are discussed above inconjunction with FIG. 55 . In at least one embodiment, application 5801further includes an OpenCL kernel 5802 with code that is to be executedon a device.

In at least one embodiment, OpenCL defines a “platform” that allows ahost to control devices connected to the host. In at least oneembodiment, an OpenCL framework provides a platform layer API and aruntime API, shown as platform API 5803 and runtime API 5805. In atleast one embodiment, runtime API 5805 uses contexts to manage executionof kernels on devices. In at least one embodiment, each identifieddevice may be associated with a respective context, which runtime API5805 may use to manage command queues, program objects, and kernelobjects, share memory objects, among other things, for that device. Inat least one embodiment, platform API 5803 exposes functions that permitdevice contexts to be used to select and initialize devices, submit workto devices via command queues, and enable data transfer to and fromdevices, among other things. In addition, OpenCL framework providesvarious built-in functions (not shown), including math functions,relational functions, and image processing functions, among others, inat least one embodiment.

In at least one embodiment, a compiler 5804 is also included in OpenCLframe-work 5810. Source code may be compiled offline prior to executingan application or online during execution of an application, in at leastone embodiment. In contrast to CUDA and ROCm, OpenCL applications in atleast one embodiment may be compiled online by compiler 5804, which isincluded to be representative of any number of compilers that may beused to compile source code and/or IR code, such as Standard PortableIntermediate Representation (“SPIR-V”) code, into binary code.Alternatively, in at least one embodiment, OpenCL ap-plications may becompiled offline, prior to execution of such applications.

In at least one embodiment, at least one component shown or describedwith respect to FIG. 58 is used to implement techniques and/or functionsdescribed in connection with FIGS. 1-35 . In at least one embodiment, atleast one element of OpenCL software stack 5800 is used to perform anapplication programming interface to indicate two or more blocks ofthreads to be scheduled in parallel. In at least one embodiment, atleast one element of OpenCL software stack 5800 is used to perform anapplication programming interface to determine which of two or moreblocks of threads to be scheduled in parallel. In at least oneembodiment, at least one element of OpenCL software stack 5800 is usedto perform an application programming interface comprising one or moreparameters to cause a scheduling policy of one or more blocks of one ormore threads to be performed. In at least one embodiment, at least oneelement of OpenCL software stack 5800 is used to perform an applicationprogramming interface comprising one or more parameters to indicate ascheduling policy of one or more blocks of one or more threads. In atleast one embodiment, at least one element of OpenCL software stack 5800is used to perform an application programming interface to indicate amaximum number of blocks of threads capable of being scheduled inparallel. In at least one embodiment, at least one element of OpenCLsoftware stack 5800 is used to perform an application programminginterface comprising one or more parameters to indicate one or moreattributes of one or more groups of blocks of one or more threads. In atleast one embodiment, at least one element of OpenCL software stack 5800is used to perform an application programming interface to indicate amaximum number of blocks of threads to be scheduled in parallel. In atleast one embodiment, at least one element of OpenCL software stack 5800is used to perform an application programming interface to cause akernel to be generated to cause two or more blocks of two or morethreads to be scheduled in parallel. In at least one embodiment, atleast one element of OpenCL software stack 5800 is used to perform anapplication programming interface comprising one or more parameters toindicate one or more limitations of one or more attributes of one ormore groups of blocks of one or more threads. In at least oneembodiment, at least one element of OpenCL software stack 5800 is usedto perform an application programming interface to indicate whether oneor more threads within two or more blocks of threads have performed abarrier instruction. In at least one embodiment, at least one element ofOpenCL software stack 5800 is used to perform an application programminginterface to cause performance of one or more threads within a group ofblocks of threads to stop at least until all threads within the group ofblocks have performed a barrier instruction. In at least one embodiment,at least one element of OpenCL software stack 5800 is used to perform anapplication programming interface to indicate whether one or morethreads within two or more blocks of threads have performed a barrierinstruction and to cause performance of one or more threads within thegroup of blocks of threads to stop at least until all threads within thegroup of blocks have performed the barrier instruction. In at least oneembodiment, at least one element of OpenCL software stack 5800 is usedto perform an application programming interface to cause memory to beshared between two or more groups of blocks of threads.

In at least one embodiment, at least one element of OpenCL softwarestack 5800 is used to perform at least one aspect described with respectto example computer system 100, example diagram 200, example diagram300, example diagram 400, example diagram 500, example process 600,example diagram 700, example application programming interface 800,example application programming interface 900, example diagram 1000,example diagram 1100, example application programming interface 1200,example application programming interface 1300, example computer system1400, example application programming interface 1500, example diagram1600, example application programming interface 1700, example computersystem 1800, example application programming interface 1900, examplecomputer system 2000, example application programming interface 2100,example diagram 2200, example diagram 2300, example diagram 2400,example diagram 2500, example application programming interface 2600,example diagram 2700, example diagram 2800, example diagram 2900,example application programming interface 3000, example applicationprogramming interface 3100, example application programming interface3200, example diagram 3300, example application programming interface3400, example software stack 3500, and/or other systems, methods, oroperations described herein.

FIG. 59 illustrates software that is supported by a programmingplatform, in accordance with at least one embodiment. In at least oneembodiment, a programming platform 5904 is configured to support variousprogramming models 5903, middlewares and/or libraries 5902, andframeworks 5901 that an application 5900 may rely upon. In at least oneembodiment, application 5900 may be an AI/ML application implementedusing, for example, a deep learning framework such as MXNet, PyTorch, orTensorFlow, which may rely on libraries such as cuDNN, NVIDIA CollectiveCommunications Library (“NCCL”), and/or NVIDA Developer Data LoadingLibrary (“DALI”) CUDA libraries to provide accelerated computing onunderlying hardware.

In at least one embodiment, programming platform 5904 may be one of aCUDA, ROCm, or OpenCL platform described above in conjunction with FIG.56 , FIG. 57 , and FIG. 58 , respectively. In at least one embodiment,programming platform 5904 supports multiple programming models 5903,which are abstractions of an underlying computing system permittingexpressions of algorithms and data structures. Programming models 5903may expose features of underlying hardware in order to improveperformance, in at least one embodiment. In at least one embodiment,programming models 5903 may include, but are not limited to, CUDA, HIP,OpenCL, C++ Accelerated Massive Parallelism (“C++ AMP”), OpenMulti-Processing (“OpenMP”), Open Accelerators (“OpenACC”), and/orVulcan Compute.

In at least one embodiment, libraries and/or middlewares 5902 provideimplementations of abstractions of programming models 5904. In at leastone embodiment, such libraries include data and programming code thatmay be used by computer programs and leveraged during softwaredevelopment. In at least one embodiment, such middlewares includesoftware that provides services to applications beyond those availablefrom programming platform 5904. In at least one embodiment, librariesand/or middlewares 5902 may include, but are not limited to, cuBLAS,cuFFT, cuRAND, and other CUDA libraries, or rocBLAS, rocFFT, rocRAND,and other ROCm libraries. In addition, in at least one embodiment,libraries and/or middlewares 5902 may include NCCL and ROCmCommunication Collectives Library (“RCCL”) libraries providingcommunication routines for GPUs, a MIOpen library for deep learningacceleration, and/or an Eigen library for linear algebra, matrix andvector operations, geometrical transformations, numerical solvers, andrelated algorithms.

In at least one embodiment, application frameworks 5901 depend onlibraries and/or middlewares 5902. In at least one embodiment, each ofapplication frameworks 5901 is a software framework used to implement astandard structure of application software. Returning to the AI/MLexample discussed above, an AI/ML application may be implemented using aframework such as Caffe, Caffe2, TensorFlow, Keras, PyTorch, or MxNetdeep learning frameworks, in at least one embodiment.

In at least one embodiment, at least one component shown or describedwith respect to FIG. 59 is used to implement techniques and/or functionsdescribed in connection with FIGS. 1-35 . In at least one embodiment,application 5900 is used to perform an application programming interfaceto indicate two or more blocks of threads to be scheduled in parallel.In at least one embodiment, application 5900 is used to perform anapplication programming interface to determine which of two or moreblocks of threads to be scheduled in parallel. In at least oneembodiment, application 5900 is used to perform an applicationprogramming interface comprising one or more parameters to cause ascheduling policy of one or more blocks of one or more threads to beperformed. In at least one embodiment, application 5900 is used toperform an application programming interface comprising one or moreparameters to indicate a scheduling policy of one or more blocks of oneor more threads. In at least one embodiment, application 5900 is used toperform an application programming interface to indicate a maximumnumber of blocks of threads capable of being scheduled in parallel. Inat least one embodiment, application 5900 is used to perform anapplication programming interface comprising one or more parameters toindicate one or more attributes of one or more groups of blocks of oneor more threads. In at least one embodiment, application 5900 is used toperform an application programming interface to indicate a maximumnumber of blocks of threads to be scheduled in parallel. In at least oneembodiment, application 5900 is used to perform an applicationprogramming interface to cause a kernel to be generated to cause two ormore blocks of two or more threads to be scheduled in parallel. In atleast one embodiment, application 5900 is used to perform an applicationprogramming interface comprising one or more parameters to indicate oneor more limitations of one or more attributes of one or more groups ofblocks of one or more threads. In at least one embodiment, application5900 is used to perform an application programming interface to indicatewhether one or more threads within two or more blocks of threads haveperformed a barrier instruction. In at least one embodiment, application5900 is used to perform an application programming interface to causeperformance of one or more threads within a group of blocks of threadsto stop at least until all threads within the group of blocks haveperformed a barrier instruction. In at least one embodiment, application5900 is used to perform an application programming interface to indicatewhether one or more threads within two or more blocks of threads haveperformed a barrier instruction and to cause performance of one or morethreads within the group of blocks of threads to stop at least until allthreads within the group of blocks have performed the barrierinstruction. In at least one embodiment, application 5900 is used toperform an application programming interface to cause memory to beshared between two or more groups of blocks of threads.

In at least one embodiment, application 5900 is used to perform at leastone aspect described with respect to example computer system 100,example diagram 200, example diagram 300, example diagram 400, examplediagram 500, example process 600, example diagram 700, exampleapplication programming interface 800, example application programminginterface 900, example diagram 1000, example diagram 1100, exampleapplication programming interface 1200, example application programminginterface 1300, example computer system 1400, example applicationprogramming interface 1500, example diagram 1600, example applicationprogramming interface 1700, example computer system 1800, exampleapplication programming interface 1900, example computer system 2000,example application programming interface 2100, example diagram 2200,example diagram 2300, example diagram 2400, example diagram 2500,example application programming interface 2600, example diagram 2700,example diagram 2800, example diagram 2900, example applicationprogramming interface 3000, example application programming interface3100, example application programming interface 3200, example diagram3300, example application programming interface 3400, example softwarestack 3500, and/or other systems, methods, or operations describedherein.

FIG. 60 illustrates compiling code to execute on one of programmingplatforms of FIGS. 55-58 , in accordance with at least one embodiment.In at least one embodiment, a compiler 6001 receives source code 6000that includes both host code as well as device code. In at least oneembodiment, complier 6001 is configured to convert source code 6000 intohost executable code 6002 for execution on a host and device executablecode 6003 for execution on a device. In at least one embodiment, sourcecode 6000 may either be compiled offline prior to execution of anapplication, or online during execution of an application.

In at least one embodiment, source code 6000 may include code in anyprogramming language supported by compiler 6001, such as C++, C,Fortran, etc. In at least one embodiment, source code 6000 may beincluded in a single-source file having a mixture of host code anddevice code, with locations of device code being indicated therein. Inat least one embodiment, a single-source file may be a .cu file thatincludes CUDA code or a .hip.cpp file that includes HIP code.Alternatively, in at least one embodiment, source code 6000 may includemultiple source code files, rather than a single-source file, into whichhost code and device code are separated.

In at least one embodiment, compiler 6001 is configured to compilesource code 6000 into host executable code 6002 for execution on a hostand device executable code 6003 for execution on a device. In at leastone embodiment, compiler 6001 performs operations including parsingsource code 6000 into an abstract system tree (AST), performingoptimizations, and generating executable code. In at least oneembodiment in which source code 6000 includes a single-source file,compiler 6001 may separate device code from host code in such asingle-source file, compile device code and host code into deviceexecutable code 6003 and host executable code 6002, respectively, andlink device executable code 6003 and host executable code 6002 togetherin a single file, as discussed in greater detail below with respect toFIG. 61 .

In at least one embodiment, host executable code 6002 and deviceexecutable code 6003 may be in any suitable format, such as binary codeand/or IR code. In the case of CUDA, host executable code 6002 mayinclude native object code and device executable code 6003 may includecode in PTX intermediate representation, in at least one embodiment. Inthe case of ROCm, both host executable code 6002 and device executablecode 6003 may include target binary code, in at least one embodiment.

In at least one embodiment, at least one component shown or describedwith respect to FIG. 60 is used to implement techniques and/or functionsdescribed in connection with FIGS. 1-35 . In at least one embodiment, atleast one of host executable code 6002 or device executable code 6003specified in source code 6000 is used to perform an applicationprogramming interface to indicate two or more blocks of threads to bescheduled in parallel. In at least one embodiment, at least one of hostexecutable code 6002 or device executable code 6003 specified in sourcecode 6000 is used to perform an application programming interface todetermine which of two or more blocks of threads to be scheduled inparallel. In at least one embodiment, at least one of host executablecode 6002 or device executable code 6003 specified in source code 6000is used to perform an application programming interface comprising oneor more parameters to cause a scheduling policy of one or more blocks ofone or more threads to be performed. In at least one embodiment, atleast one of host executable code 6002 or device executable code 6003specified in source code 6000 is used to perform an applicationprogramming interface comprising one or more parameters to indicate ascheduling policy of one or more blocks of one or more threads. In atleast one embodiment, at least one of host executable code 6002 ordevice executable code 6003 specified in source code 6000 is used toperform an application programming interface to indicate a maximumnumber of blocks of threads capable of being scheduled in parallel. Inat least one embodiment, at least one of host executable code 6002 ordevice executable code 6003 specified in source code 6000 is used toperform an application programming interface comprising one or moreparameters to indicate one or more attributes of one or more groups ofblocks of one or more threads. In at least one embodiment, at least oneof host executable code 6002 or device executable code 6003 specified insource code 6000 is used to perform an application programming interfaceto indicate a maximum number of blocks of threads to be scheduled inparallel. In at least one embodiment, at least one of host executablecode 6002 or device executable code 6003 specified in source code 6000is used to perform an application programming interface to cause akernel to be generated to cause two or more blocks of two or morethreads to be scheduled in parallel. In at least one embodiment, atleast one of host executable code 6002 or device executable code 6003specified in source code 6000 is used to perform an applicationprogramming interface comprising one or more parameters to indicate oneor more limitations of one or more attributes of one or more groups ofblocks of one or more threads. In at least one embodiment, at least oneof host executable code 6002 or device executable code 6003 specified insource code 6000 is used to perform an application programming interfaceto indicate whether one or more threads within two or more blocks ofthreads have performed a barrier instruction. In at least oneembodiment, at least one of host executable code 6002 or deviceexecutable code 6003 specified in source code 6000 is used to perform anapplication programming interface to cause performance of one or morethreads within a group of blocks of threads to stop at least until allthreads within the group of blocks have performed a barrier instruction.In at least one embodiment, at least one of host executable code 6002 ordevice executable code 6003 specified in source code 6000 is used toperform an application programming interface to indicate whether one ormore threads within two or more blocks of threads have performed abarrier instruction and to cause performance of one or more threadswithin the group of blocks of threads to stop at least until all threadswithin the group of blocks have performed the barrier instruction. In atleast one embodiment, at least one of host executable code 6002 ordevice executable code 6003 specified in source code 6000 is used toperform an application programming interface to cause memory to beshared between two or more groups of blocks of threads.

In at least one embodiment, at least one of host executable code 6002 ordevice executable code 6003 specified in source code 6000 is used toperform at least one aspect described with respect to example computersystem 100, example diagram 200, example diagram 300, example diagram400, example diagram 500, example process 600, example diagram 700,example application programming interface 800, example applicationprogramming interface 900, example diagram 1000, example diagram 1100,example application programming interface 1200, example applicationprogramming interface 1300, example computer system 1400, exampleapplication programming interface 1500, example diagram 1600, exampleapplication programming interface 1700, example computer system 1800,example application programming interface 1900, example computer system2000, example application programming interface 2100, example diagram2200, example diagram 2300, example diagram 2400, example diagram 2500,example application programming interface 2600, example diagram 2700,example diagram 2800, example diagram 2900, example applicationprogramming interface 3000, example application programming interface3100, example application programming interface 3200, example diagram3300, example application programming interface 3400, example softwarestack 3500, and/or other systems, methods, or operations describedherein.

FIG. 61 is a more detailed illustration of compiling code to execute onone of programming platforms of FIGS. 55-58 , in accordance with atleast one embodiment. In at least one embodiment, a compiler 6101 isconfigured to receive source code 6100, compile source code 6100, andoutput an executable file 6110. In at least one embodiment, source code6100 is a single-source file, such as a .cu file, a .hip.cpp file, or afile in another format, that includes both host and device code. In atleast one embodiment, compiler 6101 may be, but is not limited to, anNVIDIA CUDA compiler (“NVCC”) for compiling CUDA code in .cu files, or aHCC compiler for compiling HIP code in .hip.cpp files.

In at least one embodiment, compiler 6101 includes a compiler front end6102, a host compiler 6105, a device compiler 6106, and a linker 6109.In at least one embodiment, compiler front end 6102 is configured toseparate device code 6104 from host code 6103 in source code 6100.Device code 6104 is compiled by device compiler 6106 into deviceexecutable code 6108, which as described may include binary code or IRcode, in at least one embodiment. Separately, host code 6103 is compiledby host compiler 6105 into host executable code 6107, in at least oneembodiment. For NVCC, host compiler 6105 may be, but is not limited to,a general purpose C/C++ compiler that outputs native object code, whiledevice compiler 6106 may be, but is not limited to, a Low Level VirtualMachine (“LLVM”)-based compiler that forks a LLVM compilerinfrastructure and outputs PTX code or binary code, in at least oneembodiment. For HCC, both host compiler 6105 and device compiler 6106may be, but are not limited to, LLVM-based compilers that output targetbinary code, in at least one embodiment.

Subsequent to compiling source code 6100 into host executable code 6107and device executable code 6108, linker 6109 links host and deviceexecutable code 6107 and 6108 together in executable file 6110, in atleast one embodiment. In at least one embodiment, native object code fora host and PTX or binary code for a device may be linked together in anExecutable and Linkable Format (“ELF”) file, which is a container formatused to store object code.

In at least one embodiment, at least one component shown or describedwith respect to FIG. 61 is used to implement techniques and/or functionsdescribed in connection with FIGS. 1-35 . In at least one embodiment,executable file 6110 implemented using source code 6100 is used toperform an application programming interface to indicate two or moreblocks of threads to be scheduled in parallel. In at least oneembodiment, executable file 6110 implemented using source code 6100 isused to perform an application programming interface to determine whichof two or more blocks of threads to be scheduled in parallel. In atleast one embodiment, executable file 6110 implemented using source code6100 is used to perform an application programming interface comprisingone or more parameters to cause a scheduling policy of one or moreblocks of one or more threads to be performed. In at least oneembodiment, executable file 6110 implemented using source code 6100 isused to perform an application programming interface comprising one ormore parameters to indicate a scheduling policy of one or more blocks ofone or more threads. In at least one embodiment, executable file 6110implemented using source code 6100 is used to perform an applicationprogramming interface to indicate a maximum number of blocks of threadscapable of being scheduled in parallel. In at least one embodiment,executable file 6110 implemented using source code 6100 is used toperform an application programming interface comprising one or moreparameters to indicate one or more attributes of one or more groups ofblocks of one or more threads. In at least one embodiment, executablefile 6110 implemented using source code 6100 is used to perform anapplication programming interface to indicate a maximum number of blocksof threads to be scheduled in parallel. In at least one embodiment,executable file 6110 implemented using source code 6100 is used toperform an application programming interface to cause a kernel to begenerated to cause two or more blocks of two or more threads to bescheduled in parallel. In at least one embodiment, executable file 6110implemented using source code 6100 is used to perform an applicationprogramming interface comprising one or more parameters to indicate oneor more limitations of one or more attributes of one or more groups ofblocks of one or more threads. In at least one embodiment, executablefile 6110 implemented using source code 6100 is used to perform anapplication programming interface to indicate whether one or morethreads within two or more blocks of threads have performed a barrierinstruction. In at least one embodiment, executable file 6110implemented using source code 6100 is used to perform an applicationprogramming interface to cause performance of one or more threads withina group of blocks of threads to stop at least until all threads withinthe group of blocks have performed a barrier instruction. In at leastone embodiment, executable file 6110 implemented using source code 6100is used to perform an application programming interface to indicatewhether one or more threads within two or more blocks of threads haveperformed a barrier instruction and to cause performance of one or morethreads within the group of blocks of threads to stop at least until allthreads within the group of blocks have performed the barrierinstruction. In at least one embodiment, executable file 6110implemented using source code 6100 is used to perform an applicationprogramming interface to cause memory to be shared between two or moregroups of blocks of threads.

In at least one embodiment, executable file 6110 implemented usingsource code 6100 is used to perform at least one aspect described withrespect to example computer system 100, example diagram 200, examplediagram 300, example diagram 400, example diagram 500, example process600, example diagram 700, example application programming interface 800,example application programming interface 900, example diagram 1000,example diagram 1100, example application programming interface 1200,example application programming interface 1300, example computer system1400, example application programming interface 1500, example diagram1600, example application programming interface 1700, example computersystem 1800, example application programming interface 1900, examplecomputer system 2000, example application programming interface 2100,example diagram 2200, example diagram 2300, example diagram 2400,example diagram 2500, example application programming interface 2600,example diagram 2700, example diagram 2800, example diagram 2900,example application programming interface 3000, example applicationprogramming interface 3100, example application programming interface3200, example diagram 3300, example application programming interface3400, example software stack 3500, and/or other systems, methods, oroperations described herein.

FIG. 62 illustrates translating source code prior to compiling sourcecode, in accordance with at least one embodiment. In at least oneembodiment, source code 6200 is passed through a translation tool 6201,which translates source code 6200 into translated source code 6202. Inat least one embodiment, a compiler 6203 is used to compile translatedsource code 6202 into host executable code 6204 and device executablecode 6205 in a process that is similar to compilation of source code6000 by compiler 6001 into host executable code 6002 and deviceexecutable 6003, as discussed above in conjunction with FIG. 60 .

In at least one embodiment, a translation performed by translation tool6201 is used to port source 6200 for execution in a differentenvironment than that in which it was originally intended to run. In atleast one embodiment, translation tool 6201 may include, but is notlimited to, a HIP translator that is used to “hipify” CUDA code intendedfor a CUDA platform into HIP code that can be compiled and executed on aROCm platform. In at least one embodiment, translation of source code6200 may include parsing source code 6200 and converting calls to API(s)provided by one programming model (e.g., CUDA) into corresponding callsto API(s) provided by another programming model (e.g., HIP), asdiscussed in greater detail below in conjunction with FIGS. 63A-64 .Returning to the example of hipifying CUDA code, calls to CUDA runtimeAPI, CUDA driver API, and/or CUDA libraries may be converted tocorresponding HIP API calls, in at least one embodiment. In at least oneembodiment, automated translations performed by translation tool 6201may sometimes be incomplete, requiring additional, manual effort tofully port source code 6200.

In at least one embodiment, at least one component shown or describedwith respect to FIG. 62 is used to implement techniques and/or functionsdescribed in connection with FIGS. 1-35 . In at least one embodiment, atleast one of host executable code 6204 or device executable code 6205specified in source code 6200 is used to perform an applicationprogramming interface to indicate two or more blocks of threads to bescheduled in parallel. In at least one embodiment, at least one of hostexecutable code 6204 or device executable code 6205 specified in sourcecode 6200 is used to perform an application programming interface todetermine which of two or more blocks of threads to be scheduled inparallel. In at least one embodiment, at least one of host executablecode 6204 or device executable code 6205 specified in source code 6200is used to perform an application programming interface comprising oneor more parameters to cause a scheduling policy of one or more blocks ofone or more threads to be performed. In at least one embodiment, atleast one of host executable code 6204 or device executable code 6205specified in source code 6200 is used to perform an applicationprogramming interface comprising one or more parameters to indicate ascheduling policy of one or more blocks of one or more threads. In atleast one embodiment, at least one of host executable code 6204 ordevice executable code 6205 specified in source code 6200 is used toperform an application programming interface to indicate a maximumnumber of blocks of threads capable of being scheduled in parallel. Inat least one embodiment, at least one of host executable code 6204 ordevice executable code 6205 specified in source code 6200 is used toperform an application programming interface comprising one or moreparameters to indicate one or more attributes of one or more groups ofblocks of one or more threads. In at least one embodiment, at least oneof host executable code 6204 or device executable code 6205 specified insource code 6200 is used to perform an application programming interfaceto indicate a maximum number of blocks of threads to be scheduled inparallel. In at least one embodiment, at least one of host executablecode 6204 or device executable code 6205 specified in source code 6200is used to perform an application programming interface to cause akernel to be generated to cause two or more blocks of two or morethreads to be scheduled in parallel. In at least one embodiment, atleast one of host executable code 6204 or device executable code 6205specified in source code 6200 is used to perform an applicationprogramming interface comprising one or more parameters to indicate oneor more limitations of one or more attributes of one or more groups ofblocks of one or more threads. In at least one embodiment, at least oneof host executable code 6204 or device executable code 6205 specified insource code 6200 is used to perform an application programming interfaceto indicate whether one or more threads within two or more blocks ofthreads have performed a barrier instruction. In at least oneembodiment, at least one of host executable code 6204 or deviceexecutable code 6205 specified in source code 6200 is used to perform anapplication programming interface to cause performance of one or morethreads within a group of blocks of threads to stop at least until allthreads within the group of blocks have performed a barrier instruction.In at least one embodiment, at least one of host executable code 6204 ordevice executable code 6205 specified in source code 6200 is used toperform an application programming interface to indicate whether one ormore threads within two or more blocks of threads have performed abarrier instruction and to cause performance of one or more threadswithin the group of blocks of threads to stop at least until all threadswithin the group of blocks have performed the barrier instruction. In atleast one embodiment, at least one of host executable code 6204 ordevice executable code 6205 specified in source code 6200 is used toperform an application programming interface to cause memory to beshared between two or more groups of blocks of threads.

In at least one embodiment, at least one of host executable code 6204 ordevice executable code 6205 specified in source code 6200 is used toperform at least one aspect described with respect to example computersystem 100, example diagram 200, example diagram 300, example diagram400, example diagram 500, example process 600, example diagram 700,example application programming interface 800, example applicationprogramming interface 900, example diagram 1000, example diagram 1100,example application programming interface 1200, example applicationprogramming interface 1300, example computer system 1400, exampleapplication programming interface 1500, example diagram 1600, exampleapplication programming interface 1700, example computer system 1800,example application programming interface 1900, example computer system2000, example application programming interface 2100, example diagram2200, example diagram 2300, example diagram 2400, example diagram 2500,example application programming interface 2600, example diagram 2700,example diagram 2800, example diagram 2900, example applicationprogramming interface 3000, example application programming interface3100, example application programming interface 3200, example diagram3300, example application programming interface 3400, example softwarestack 3500, and/or other systems, methods, or operations describedherein.

Configuring GPUs for General-Purpose Computing

The following figures set forth, without limitation, exemplaryarchitectures for compiling and executing compute source code, inaccordance with at least one embodiment.

FIG. 63A illustrates a system 63A00 configured to compile and executeCUDA source code 6310 using different types of processing units, inaccordance with at least one embodiment. In at least one embodiment,system 63A00 includes, without limitation, CUDA source code 6310, a CUDAcompiler 6350, host executable code 6370(1), host executable code6370(2), CUDA device executable code 6384, a CPU 6390, a CUDA-enabledGPU 6394, a GPU 6392, a CUDA to HIP translation tool 6320, HIP sourcecode 6330, a HIP compiler driver 6340, an HCC 6360, and HCC deviceexecutable code 6382.

In at least one embodiment, CUDA source code 6310 is a collection ofhuman-readable code in a CUDA programming language. In at least oneembodiment, CUDA code is human-readable code in a CUDA programminglanguage. In at least one embodiment, a CUDA programming language is anextension of the C++ programming language that includes, withoutlimitation, mechanisms to define device code and distinguish betweendevice code and host code. In at least one embodiment, device code issource code that, after compilation, is executable in parallel on adevice. In at least one embodiment, a device may be a processor that isoptimized for parallel instruction processing, such as CUDA-enabled GPU6390, GPU 63192, or another GPGPU, etc. In at least one embodiment, hostcode is source code that, after compilation, is executable on a host. Inat least one embodiment, a host is a processor that is optimized forsequential instruction processing, such as CPU 6390.

In at least one embodiment, CUDA source code 6310 includes, withoutlimitation, any number (including zero) of global functions 6312, anynumber (including zero) of device functions 6314, any number (includingzero) of host functions 6316, and any number (including zero) ofhost/device functions 6318. In at least one embodiment, global functions6312, device functions 6314, host functions 6316, and host/devicefunctions 6318 may be mixed in CUDA source code 6310. In at least oneembodiment, each of global functions 6312 is executable on a device andcallable from a host. In at least one embodiment, one or more of globalfunctions 6312 may therefore act as entry points to a device. In atleast one embodiment, each of global functions 6312 is a kernel. In atleast one embodiment and in a technique known as dynamic parallelism,one or more of global functions 6312 defines a kernel that is executableon a device and callable from such a device. In at least one embodiment,a kernel is executed N (where N is any positive integer) times inparallel by N different threads on a device during execution.

In at least one embodiment, each of device functions 6314 is executed ona device and callable from such a device only. In at least oneembodiment, each of host functions 6316 is executed on a host andcallable from such a host only. In at least one embodiment, each ofhost/device functions 6316 defines both a host version of a functionthat is executable on a host and callable from such a host only and adevice version of the function that is executable on a device andcallable from such a device only.

In at least one embodiment, CUDA source code 6310 may also include,without limitation, any number of calls to any number of functions thatare defined via a CUDA runtime API 6302. In at least one embodiment,CUDA runtime API 6302 may include, without limitation, any number offunctions that execute on a host to allocate and deallocate devicememory, transfer data between host memory and device memory, managesystems with multiple devices, etc. In at least one embodiment, CUDAsource code 6310 may also include any number of calls to any number offunctions that are specified in any number of other CUDA APIs. In atleast one embodiment, a CUDA API may be any API that is designed for useby CUDA code. In at least one embodiment, CUDA APIs include, withoutlimitation, CUDA runtime API 6302, a CUDA driver API, APIs for anynumber of CUDA libraries, etc. In at least one embodiment and relativeto CUDA runtime API 6302, a CUDA driver API is a lower-level API butprovides finer-grained control of a device. In at least one embodiment,examples of CUDA libraries include, without limitation, cuBLAS, cuFFT,cuRAND, cuDNN, etc.

In at least one embodiment, CUDA compiler 6350 compiles input CUDA code(e.g., CUDA source code 6310) to generate host executable code 6370(1)and CUDA device executable code 6384. In at least one embodiment, CUDAcompiler 6350 is NVCC. In at least one embodiment, host executable code6370(1) is a compiled version of host code included in input source codethat is executable on CPU 6390. In at least one embodiment, CPU 6390 maybe any processor that is optimized for sequential instructionprocessing.

In at least one embodiment, CUDA device executable code 6384 is acompiled version of device code included in input source code that isexecutable on CUDA-enabled GPU 6394. In at least one embodiment, CUDAdevice executable code 6384 includes, without limitation, binary code.In at least one embodiment, CUDA device executable code 6384 includes,without limitation, IR code, such as PTX code, that is further compiledat runtime into binary code for a specific target device (e.g.,CUDA-enabled GPU 6394) by a device driver. In at least one embodiment,CUDA-enabled GPU 6394 may be any processor that is optimized forparallel instruction processing and that supports CUDA. In at least oneembodiment, CUDA-enabled GPU 6394 is developed by NVIDIA Corporation ofSanta Clara, CA.

In at least one embodiment, CUDA to HIP translation tool 6320 isconfigured to translate CUDA source code 6310 to functionally similarHIP source code 6330. In a least one embodiment, HIP source code 6330 isa collection of human-readable code in a HIP programming language. In atleast one embodiment, HIP code is human-readable code in a HIPprogramming language. In at least one embodiment, a HIP programminglanguage is an extension of the C++ programming language that includes,without limitation, functionally similar versions of CUDA mechanisms todefine device code and distinguish between device code and host code. Inat least one embodiment, a HIP programming language may include a subsetof functionality of a CUDA programming language. In at least oneembodiment, for example, a HIP programming language includes, withoutlimitation, mechanism(s) to define global functions 6312, but such a HIPprogramming language may lack support for dynamic parallelism andtherefore global functions 6312 defined in HIP code may be callable froma host only.

In at least one embodiment, HIP source code 6330 includes, withoutlimitation, any number (including zero) of global functions 6312, anynumber (including zero) of device functions 6314, any number (includingzero) of host functions 6316, and any number (including zero) ofhost/device functions 6318. In at least one embodiment, HIP source code6330 may also include any number of calls to any number of functionsthat are specified in a HIP runtime API 6332. In at least oneembodiment, HIP runtime API 6332 includes, without limitation,functionally similar versions of a subset of functions included in CUDAruntime API 6302. In at least one embodiment, HIP source code 6330 mayalso include any number of calls to any number of functions that arespecified in any number of other HIP APIs. In at least one embodiment, aHIP API may be any API that is designed for use by HIP code and/or ROCm.In at least one embodiment, HIP APIs include, without limitation, HIPruntime API 6332, a HIP driver API, APIs for any number of HIPlibraries, APIs for any number of ROCm libraries, etc.

In at least one embodiment, CUDA to HIP translation tool 6320 convertseach kernel call in CUDA code from a CUDA syntax to a HIP syntax andconverts any number of other CUDA calls in CUDA code to any number ofother functionally similar HIP calls. In at least one embodiment, a CUDAcall is a call to a function specified in a CUDA API, and a HIP call isa call to a function specified in a HIP API. In at least one embodiment,CUDA to HIP translation tool 6320 converts any number of calls tofunctions specified in CUDA runtime API 6302 to any number of calls tofunctions specified in HIP runtime API 6332.

In at least one embodiment, CUDA to HIP translation tool 6320 is a toolknown as hipify-perl that executes a text-based translation process. Inat least one embodiment, CUDA to HIP translation tool 6320 is a toolknown as hipify-clang that, relative to hipify-perl, executes a morecomplex and more robust translation process that involves parsing CUDAcode using clang (a compiler front-end) and then translating resultingsymbols. In at least one embodiment, properly converting CUDA code toHIP code may require modifications (e.g., manual edits) in addition tothose performed by CUDA to HIP translation tool 6320.

In at least one embodiment, HIP compiler driver 6340 is a front end thatdetermines a target device 6346 and then configures a compiler that iscompatible with target device 6346 to compile HIP source code 6330. Inat least one embodiment, target device 6346 is a processor that isoptimized for parallel instruction processing. In at least oneembodiment, HIP compiler driver 6340 may determine target device 6346 inany technically feasible fashion.

In at least one embodiment, if target device 6346 is compatible withCUDA (e.g., CUDA-enabled GPU 6394), then HIP compiler driver 6340generates a HIP/NVCC compilation command 6342. In at least oneembodiment and as described in greater detail in conjunction with FIG.63B, HIP/NVCC compilation command 6342 configures CUDA compiler 6350 tocompile HIP source code 6330 using, without limitation, a HIP to CUDAtranslation header and a CUDA runtime library. In at least oneembodiment and in response to HIP/NVCC compilation command 6342, CUDAcompiler 6350 generates host executable code 6370(1) and CUDA deviceexecutable code 6384.

In at least one embodiment, if target device 6346 is not compatible withCUDA, then HIP compiler driver 6340 generates a HIP/HCC compilationcommand 6344. In at least one embodiment and as described in greaterdetail in conjunction with FIG. 63C, HIP/HCC compilation command 6344configures HCC 6360 to compile HIP source code 6330 using, withoutlimitation, an HCC header and a HIP/HCC runtime library. In at least oneembodiment and in response to HIP/HCC compilation command 6344, HCC 6360generates host executable code 6370(2) and HCC device executable code6382. In at least one embodiment, HCC device executable code 6382 is acompiled version of device code included in HIP source code 6330 that isexecutable on GPU 6392. In at least one embodiment, GPU 6392 may be anyprocessor that is optimized for parallel instruction processing, is notcompatible with CUDA, and is compatible with HCC. In at least oneembodiment, GPU 6392 is developed by AMD Corporation of Santa Clara, CA.In at least one embodiment GPU, 6392 is a non-CUDA-enabled GPU 6392.

For explanatory purposes only, three different flows that may beimplemented in at least one embodiment to compile CUDA source code 6310for execution on CPU 6390 and different devices are depicted in FIG.63A. In at least one embodiment, a direct CUDA flow compiles CUDA sourcecode 6310 for execution on CPU 6390 and CUDA-enabled GPU 6394 withouttranslating CUDA source code 6310 to HIP source code 6330. In at leastone embodiment, an indirect CUDA flow translates CUDA source code 6310to HIP source code 6330 and then compiles HIP source code 6330 forexecution on CPU 6390 and CUDA-enabled GPU 6394. In at least oneembodiment, a CUDA/HCC flow translates CUDA source code 6310 to HIPsource code 6330 and then compiles HIP source code 6330 for execution onCPU 6390 and GPU 6392.

A direct CUDA flow that may be implemented in at least one embodiment isdepicted via dashed lines and a series of bubbles annotated A1-A3. In atleast one embodiment and as depicted with bubble annotated A1, CUDAcompiler 6350 receives CUDA source code 6310 and a CUDA compile command6348 that configures CUDA compiler 6350 to compile CUDA source code6310. In at least one embodiment, CUDA source code 6310 used in a directCUDA flow is written in a CUDA programming language that is based on aprogramming language other than C++ (e.g., C, Fortran, Python, Java,etc.). In at least one embodiment and in response to CUDA compilecommand 6348, CUDA compiler 6350 generates host executable code 6370(1)and CUDA device executable code 6384 (depicted with bubble annotatedA2). In at least one embodiment and as depicted with bubble annotatedA3, host executable code 6370(1) and CUDA device executable code 6384may be executed on, respectively, CPU 6390 and CUDA-enabled GPU 6394. Inat least one embodiment, CUDA device executable code 6384 includes,without limitation, binary code. In at least one embodiment, CUDA deviceexecutable code 6384 includes, without limitation, PTX code and isfurther compiled into binary code for a specific target device atruntime.

An indirect CUDA flow that may be implemented in at least one embodimentis depicted via dotted lines and a series of bubbles annotated B1-B6. Inat least one embodiment and as depicted with bubble annotated B1, CUDAto HIP translation tool 6320 receives CUDA source code 6310. In at leastone embodiment and as depicted with bubble annotated B2, CUDA to HIPtranslation tool 6320 translates CUDA source code 6310 to HIP sourcecode 6330. In at least one embodiment and as depicted with bubbleannotated B3, HIP compiler driver 6340 receives HIP source code 6330 anddetermines that target device 6346 is CUDA-enabled.

In at least one embodiment and as depicted with bubble annotated B4, HIPcompiler driver 6340 generates HIP/NVCC compilation command 6342 andtransmits both HIP/NVCC compilation command 6342 and HIP source code6330 to CUDA compiler 6350. In at least one embodiment and as describedin greater detail in conjunction with FIG. 63B, HIP/NVCC compilationcommand 6342 configures CUDA compiler 6350 to compile HIP source code6330 using, without limitation, a HIP to CUDA translation header and aCUDA runtime library. In at least one embodiment and in response toHIP/NVCC compilation command 6342, CUDA compiler 6350 generates hostexecutable code 6370(1) and CUDA device executable code 6384 (depictedwith bubble annotated B5). In at least one embodiment and as depictedwith bubble annotated B6, host executable code 6370(1) and CUDA deviceexecutable code 6384 may be executed on, respectively, CPU 6390 andCUDA-enabled GPU 6394. In at least one embodiment, CUDA deviceexecutable code 6384 includes, without limitation, binary code. In atleast one embodiment, CUDA device executable code 6384 includes, withoutlimitation, PTX code and is further compiled into binary code for aspecific target device at runtime.

A CUDA/HCC flow that may be implemented in at least one embodiment isdepicted via solid lines and a series of bubbles annotated C1-C6. In atleast one embodiment and as depicted with bubble annotated C1, CUDA toHIP translation tool 6320 receives CUDA source code 6310. In at leastone embodiment and as depicted with bubble annotated C2, CUDA to HIPtranslation tool 6320 translates CUDA source code 6310 to HIP sourcecode 6330. In at least one embodiment and as depicted with bubbleannotated C3, HIP compiler driver 6340 receives HIP source code 6330 anddetermines that target device 6346 is not CUDA-enabled.

In at least one embodiment, HIP compiler driver 6340 generates HIP/HCCcompilation command 6344 and transmits both HIP/HCC compilation command6344 and HIP source code 6330 to HCC 6360 (depicted with bubbleannotated C4). In at least one embodiment and as described in greaterdetail in conjunction with FIG. 63C, HIP/HCC compilation command 6344configures HCC 6360 to compile HIP source code 6330 using, withoutlimitation, an HCC header and a HIP/HCC runtime library. In at least oneembodiment and in response to HIP/HCC compilation command 6344, HCC 6360generates host executable code 6370(2) and HCC device executable code6382 (depicted with bubble annotated C5). In at least one embodiment andas depicted with bubble annotated C6, host executable code 6370(2) andHCC device executable code 6382 may be executed on, respectively, CPU6390 and GPU 6392.

In at least one embodiment, after CUDA source code 6310 is translated toHIP source code 6330, HIP compiler driver 6340 may subsequently be usedto generate executable code for either CUDA-enabled GPU 6394 or GPU 6392without re-executing CUDA to HIP translation tool 6320. In at least oneembodiment, CUDA to HIP translation tool 6320 translates CUDA sourcecode 6310 to HIP source code 6330 that is then stored in memory. In atleast one embodiment, HIP compiler driver 6340 then configures HCC 6360to generate host executable code 6370(2) and HCC device executable code6382 based on HIP source code 6330. In at least one embodiment, HIPcompiler driver 6340 subsequently configures CUDA compiler 6350 togenerate host executable code 6370(1) and CUDA device executable code6384 based on stored HIP source code 6330.

In at least one embodiment, at least one component shown or describedwith respect to FIG. 63A is used to implement techniques and/orfunctions described in connection with FIGS. 1-35 . In at least oneembodiment, at least one element of system 6300 is used to perform anapplication programming interface to indicate two or more blocks ofthreads to be scheduled in parallel. In at least one embodiment, atleast one element of system 6300 is used to perform an applicationprogramming interface to determine which of two or more blocks ofthreads to be scheduled in parallel. In at least one embodiment, atleast one element of system 6300 is used to perform an applicationprogramming interface comprising one or more parameters to cause ascheduling policy of one or more blocks of one or more threads to beperformed. In at least one embodiment, at least one element of system6300 is used to perform an application programming interface comprisingone or more parameters to indicate a scheduling policy of one or moreblocks of one or more threads. In at least one embodiment, at least oneelement of system 6300 is used to perform an application programminginterface to indicate a maximum number of blocks of threads capable ofbeing scheduled in parallel. In at least one embodiment, at least oneelement of system 6300 is used to perform an application programminginterface comprising one or more parameters to indicate one or moreattributes of one or more groups of blocks of one or more threads. In atleast one embodiment, at least one element of system 6300 is used toperform an application programming interface to indicate a maximumnumber of blocks of threads to be scheduled in parallel. In at least oneembodiment, at least one element of system 6300 is used to perform anapplication programming interface to cause a kernel to be generated tocause two or more blocks of two or more threads to be scheduled inparallel. In at least one embodiment, at least one element of system6300 is used to perform an application programming interface comprisingone or more parameters to indicate one or more limitations of one ormore attributes of one or more groups of blocks of one or more threads.In at least one embodiment, at least one element of system 6300 is usedto perform an application programming interface to indicate whether oneor more threads within two or more blocks of threads have performed abarrier instruction. In at least one embodiment, at least one element ofsystem 6300 is used to perform an application programming interface tocause performance of one or more threads within a group of blocks ofthreads to stop at least until all threads within the group of blockshave performed a barrier instruction. In at least one embodiment, atleast one element of system 6300 is used to perform an applicationprogramming interface to indicate whether one or more threads within twoor more blocks of threads have performed a barrier instruction and tocause performance of one or more threads within the group of blocks ofthreads to stop at least until all threads within the group of blockshave performed the barrier instruction. In at least one embodiment, atleast one element of system 6300 is used to perform an applicationprogramming interface to cause memory to be shared between two or moregroups of blocks of threads.

In at least one embodiment, at least one element of system 6300 is usedto perform at least one aspect described with respect to examplecomputer system 100, example diagram 200, example diagram 300, examplediagram 400, example diagram 500, example process 600, example diagram700, example application programming interface 800, example applicationprogramming interface 900, example diagram 1000, example diagram 1100,example application programming interface 1200, example applicationprogramming interface 1300, example computer system 1400, exampleapplication programming interface 1500, example diagram 1600, exampleapplication programming interface 1700, example computer system 1800,example application programming interface 1900, example computer system2000, example application programming interface 2100, example diagram2200, example diagram 2300, example diagram 2400, example diagram 2500,example application programming interface 2600, example diagram 2700,example diagram 2800, example diagram 2900, example applicationprogramming interface 3000, example application programming interface3100, example application programming interface 3200, example diagram3300, example application programming interface 3400, example softwarestack 3500, and/or other systems, methods, or operations describedherein.

FIG. 63B illustrates a system 6304 configured to compile and executeCUDA source code 6310 of FIG. 63A using CPU 6390 and CUDA-enabled GPU6394, in accordance with at least one embodiment. In at least oneembodiment, system 6304 includes, without limitation, CUDA source code6310, CUDA to HIP translation tool 6320, HIP source code 6330, HIPcompiler driver 6340, CUDA compiler 6350, host executable code 6370(1),CUDA device executable code 6384, CPU 6390, and CUDA-enabled GPU 6394.

In at least one embodiment and as described previously herein inconjunction with FIG. 63A, CUDA source code 6310 includes, withoutlimitation, any number (including zero) of global functions 6312, anynumber (including zero) of device functions 6314, any number (includingzero) of host functions 6316, and any number (including zero) ofhost/device functions 6318. In at least one embodiment, CUDA source code6310 also includes, without limitation, any number of calls to anynumber of functions that are specified in any number of CUDA APIs.

In at least one embodiment, CUDA to HIP translation tool 6320 translatesCUDA source code 6310 to HIP source code 6330. In at least oneembodiment, CUDA to HIP translation tool 6320 converts each kernel callin CUDA source code 6310 from a CUDA syntax to a HIP syntax and convertsany number of other CUDA calls in CUDA source code 6310 to any number ofother functionally similar HIP calls.

In at least one embodiment, HIP compiler driver 6340 determines thattarget device 6346 is CUDA-enabled and generates HIP/NVCC compilationcommand 6342. In at least one embodiment, HIP compiler driver 6340 thenconfigures CUDA compiler 6350 via HIP/NVCC compilation command 6342 tocompile HIP source code 6330. In at least one embodiment, HIP compilerdriver 6340 provides access to a HIP to CUDA translation header 6352 aspart of configuring CUDA compiler 6350. In at least one embodiment, HIPto CUDA translation header 6352 translates any number of mechanisms(e.g., functions) specified in any number of HIP APIs to any number ofmechanisms specified in any number of CUDA APIs. In at least oneembodiment, CUDA compiler 6350 uses HIP to CUDA translation header 6352in conjunction with a CUDA runtime library 6354 corresponding to CUDAruntime API 6302 to generate host executable code 6370(1) and CUDAdevice executable code 6384. In at least one embodiment, host executablecode 6370(1) and CUDA device executable code 6384 may then be executedon, respectively, CPU 6390 and CUDA-enabled GPU 6394. In at least oneembodiment, CUDA device executable code 6384 includes, withoutlimitation, binary code. In at least one embodiment, CUDA deviceexecutable code 6384 includes, without limitation, PTX code and isfurther compiled into binary code for a specific target device atruntime.

In at least one embodiment, at least one component shown or describedwith respect to FIG. 63B is used to implement techniques and/orfunctions described in connection with FIGS. 1-35 . In at least oneembodiment, at least one element of system 6304 is used to perform anapplication programming interface to indicate two or more blocks ofthreads to be scheduled in parallel. In at least one embodiment, atleast one element of system 6304 is used to perform an applicationprogramming interface to determine which of two or more blocks ofthreads to be scheduled in parallel. In at least one embodiment, atleast one element of system 6304 is used to perform an applicationprogramming interface comprising one or more parameters to cause ascheduling policy of one or more blocks of one or more threads to beperformed. In at least one embodiment, at least one element of system6304 is used to perform an application programming interface comprisingone or more parameters to indicate a scheduling policy of one or moreblocks of one or more threads. In at least one embodiment, at least oneelement of system 6304 is used to perform an application programminginterface to indicate a maximum number of blocks of threads capable ofbeing scheduled in parallel. In at least one embodiment, at least oneelement of system 6304 is used to perform an application programminginterface comprising one or more parameters to indicate one or moreattributes of one or more groups of blocks of one or more threads. In atleast one embodiment, at least one element of system 6304 is used toperform an application programming interface to indicate a maximumnumber of blocks of threads to be scheduled in parallel. In at least oneembodiment, at least one element of system 6304 is used to perform anapplication programming interface to cause a kernel to be generated tocause two or more blocks of two or more threads to be scheduled inparallel. In at least one embodiment, at least one element of system6304 is used to perform an application programming interface comprisingone or more parameters to indicate one or more limitations of one ormore attributes of one or more groups of blocks of one or more threads.In at least one embodiment, at least one element of system 6304 is usedto perform an application programming interface to indicate whether oneor more threads within two or more blocks of threads have performed abarrier instruction. In at least one embodiment, at least one element ofsystem 6304 is used to perform an application programming interface tocause performance of one or more threads within a group of blocks ofthreads to stop at least until all threads within the group of blockshave performed a barrier instruction. In at least one embodiment, atleast one element of system 6304 is used to perform an applicationprogramming interface to indicate whether one or more threads within twoor more blocks of threads have performed a barrier instruction and tocause performance of one or more threads within the group of blocks ofthreads to stop at least until all threads within the group of blockshave performed the barrier instruction. In at least one embodiment, atleast one element of system 6304 is used to perform an applicationprogramming interface to cause memory to be shared between two or moregroups of blocks of threads.

In at least one embodiment, at least one element of system 6304 is usedto perform at least one aspect described with respect to examplecomputer system 100, example diagram 200, example diagram 300, examplediagram 400, example diagram 500, example process 600, example diagram700, example application programming interface 800, example applicationprogramming interface 900, example diagram 1000, example diagram 1100,example application programming interface 1200, example applicationprogramming interface 1300, example computer system 1400, exampleapplication programming interface 1500, example diagram 1600, exampleapplication programming interface 1700, example computer system 1800,example application programming interface 1900, example computer system2000, example application programming interface 2100, example diagram2200, example diagram 2300, example diagram 2400, example diagram 2500,example application programming interface 2600, example diagram 2700,example diagram 2800, example diagram 2900, example applicationprogramming interface 3000, example application programming interface3100, example application programming interface 3200, example diagram3300, example application programming interface 3400, example softwarestack 3500, and/or other systems, methods, or operations describedherein.

FIG. 63C illustrates a system 6306 configured to compile and executeCUDA source code 6310 of FIG. 63A using CPU 6390 and non-CUDA-enabledGPU 6392, in accordance with at least one embodiment. In at least oneembodiment, system 6306 includes, without limitation, CUDA source code6310, CUDA to HIP translation tool 6320, HIP source code 6330, HIPcompiler driver 6340, HCC 6360, host executable code 6370(2), HCC deviceexecutable code 6382, CPU 6390, and GPU 6392.

In at least one embodiment and as described previously herein inconjunction with FIG. 63A, CUDA source code 6310 includes, withoutlimitation, any number (including zero) of global functions 6312, anynumber (including zero) of device functions 6314, any number (includingzero) of host functions 6316, and any number (including zero) ofhost/device functions 6318. In at least one embodiment, CUDA source code6310 also includes, without limitation, any number of calls to anynumber of functions that are specified in any number of CUDA APIs.

In at least one embodiment, CUDA to HIP translation tool 6320 translatesCUDA source code 6310 to HIP source code 6330. In at least oneembodiment, CUDA to HIP translation tool 6320 converts each kernel callin CUDA source code 6310 from a CUDA syntax to a HIP syntax and convertsany number of other CUDA calls in source code 6310 to any number ofother functionally similar HIP calls.

In at least one embodiment, HIP compiler driver 6340 subsequentlydetermines that target device 6346 is not CUDA-enabled and generatesHIP/HCC compilation command 6344. In at least one embodiment, HIPcompiler driver 6340 then configures HCC 6360 to execute HIP/HCCcompilation command 6344 to compile HIP source code 6330. In at leastone embodiment, HIP/HCC compilation command 6344 configures HCC 6360 touse, without limitation, a HIP/HCC runtime library 6358 and an HCCheader 6356 to generate host executable code 6370(2) and HCC deviceexecutable code 6382. In at least one embodiment, HIP/HCC runtimelibrary 6358 corresponds to HIP runtime API 6332. In at least oneembodiment, HCC header 6356 includes, without limitation, any number andtype of interoperability mechanisms for HIP and HCC. In at least oneembodiment, host executable code 6370(2) and HCC device executable code6382 may be executed on, respectively, CPU 6390 and GPU 6392.

In at least one embodiment, at least one component shown or describedwith respect to FIG. 63C is used to implement techniques and/orfunctions described in connection with FIGS. 1-35 . In at least oneembodiment, at least one element of system 6306 is used to perform anapplication programming interface to indicate two or more blocks ofthreads to be scheduled in parallel. In at least one embodiment, atleast one element of system 6306 is used to perform an applicationprogramming interface to determine which of two or more blocks ofthreads to be scheduled in parallel. In at least one embodiment, atleast one element of system 6306 is used to perform an applicationprogramming interface comprising one or more parameters to cause ascheduling policy of one or more blocks of one or more threads to beperformed. In at least one embodiment, at least one element of system6306 is used to perform an application programming interface comprisingone or more parameters to indicate a scheduling policy of one or moreblocks of one or more threads. In at least one embodiment, at least oneelement of system 6306 is used to perform an application programminginterface to indicate a maximum number of blocks of threads capable ofbeing scheduled in parallel. In at least one embodiment, at least oneelement of system 6306 is used to perform an application programminginterface comprising one or more parameters to indicate one or moreattributes of one or more groups of blocks of one or more threads. In atleast one embodiment, at least one element of system 6306 is used toperform an application programming interface to indicate a maximumnumber of blocks of threads to be scheduled in parallel. In at least oneembodiment, at least one element of system 6306 is used to perform anapplication programming interface to cause a kernel to be generated tocause two or more blocks of two or more threads to be scheduled inparallel. In at least one embodiment, at least one element of system6306 is used to perform an application programming interface comprisingone or more parameters to indicate one or more limitations of one ormore attributes of one or more groups of blocks of one or more threads.In at least one embodiment, at least one element of system 6306 is usedto perform an application programming interface to indicate whether oneor more threads within two or more blocks of threads have performed abarrier instruction. In at least one embodiment, at least one element ofsystem 6306 is used to perform an application programming interface tocause performance of one or more threads within a group of blocks ofthreads to stop at least until all threads within the group of blockshave performed a barrier instruction. In at least one embodiment, atleast one element of system 6306 is used to perform an applicationprogramming interface to indicate whether one or more threads within twoor more blocks of threads have performed a barrier instruction and tocause performance of one or more threads within the group of blocks ofthreads to stop at least until all threads within the group of blockshave performed the barrier instruction. In at least one embodiment, atleast one element of system 6306 is used to perform an applicationprogramming interface to cause memory to be shared between two or moregroups of blocks of threads.

In at least one embodiment, at least one element of system 6306 is usedto perform at least one aspect described with respect to examplecomputer system 100, example diagram 200, example diagram 300, examplediagram 400, example diagram 500, example process 600, example diagram700, example application programming interface 800, example applicationprogramming interface 900, example diagram 1000, example diagram 1100,example application programming interface 1200, example applicationprogramming interface 1300, example computer system 1400, exampleapplication programming interface 1500, example diagram 1600, exampleapplication programming interface 1700, example computer system 1800,example application programming interface 1900, example computer system2000, example application programming interface 2100, example diagram2200, example diagram 2300, example diagram 2400, example diagram 2500,example application programming interface 2600, example diagram 2700,example diagram 2800, example diagram 2900, example applicationprogramming interface 3000, example application programming interface3100, example application programming interface 3200, example diagram3300, example application programming interface 3400, example softwarestack 3500, and/or other systems, methods, or operations describedherein.

FIG. 64 illustrates an exemplary kernel translated by CUDA-to-HIPtranslation tool 6320 of FIG. 63C, in accordance with at least oneembodiment. In at least one embodiment, CUDA source code 6310 partitionsan overall problem that a given kernel is designed to solve intorelatively coarse sub-problems that can independently be solved usingthread blocks. In at least one embodiment, each thread block includes,without limitation, any number of threads. In at least one embodiment,each sub-problem is partitioned into relatively fine pieces that can besolved cooperatively in parallel by threads within a thread block. In atleast one embodiment, threads within a thread block can cooperate bysharing data through shared memory and by synchronizing execution tocoordinate memory accesses.

In at least one embodiment, CUDA source code 6310 organizes threadblocks associated with a given kernel into a one-dimensional, atwo-dimensional, or a three-dimensional grid of thread blocks. In atleast one embodiment, each thread block includes, without limitation,any number of threads, and a grid includes, without limitation, anynumber of thread blocks.

In at least one embodiment, a kernel is a function in device code thatis defined using a “global” declaration specifier. In at least oneembodiment, the dimension of a grid that executes a kernel for a givenkernel call and associated streams are specified using a CUDA kernellaunch syntax 6410. In at least one embodiment, CUDA kernel launchsyntax 6410 is specified as “KernelName<<<GridSize, BlockSize,SharedMemorySize, Stream>>>(KernelArguments);”. In at least oneembodiment, an execution configuration syntax is a “<<< . . . >>>”construct that is inserted between a kernel name (“KernelName”) and aparenthesized list of kernel arguments (“KernelArguments”). In at leastone embodiment, CUDA kernel launch syntax 6410 includes, withoutlimitation, a CUDA launch function syntax instead of an executionconfiguration syntax.

In at least one embodiment, “GridSize” is of a type dim3 and specifiesthe dimension and size of a grid. In at least one embodiment, type dim3is a CUDA-defined structure that includes, without limitation, unsignedintegers x, y, and z. In at least one embodiment, if z is not specified,then z defaults to one. In at least one embodiment, if y is notspecified, then y defaults to one. In at least one embodiment, thenumber of thread blocks in a grid is equal to the product of GridSize.x,GridSize.y, and GridSize.z. In at least one embodiment, “BlockSize” isof type dim3 and specifies the dimension and size of each thread block.In at least one embodiment, the number of threads per thread block isequal to the product of BlockSize.x, BlockSize.y, and BlockSize.z. In atleast one embodiment, each thread that executes a kernel is given aunique thread ID that is accessible within the kernel through a built-invariable (e.g., “threadIdx”).

In at least one embodiment and with respect to CUDA kernel launch syntax6410, “SharedMemorySize” is an optional argument that specifies a numberof bytes in a shared memory that is dynamically allocated per threadblock for a given kernel call in addition to statically allocatedmemory. In at least one embodiment and with respect to CUDA kernellaunch syntax 6410, SharedMemorySize defaults to zero. In at least oneembodiment and with respect to CUDA kernel launch syntax 6410, “Stream”is an optional argument that specifies an associated stream and defaultsto zero to specify a default stream. In at least one embodiment, astream is a sequence of commands (possibly issued by different hostthreads) that execute in order. In at least one embodiment, differentstreams may execute commands out of order with respect to one another orconcurrently.

In at least one embodiment, CUDA source code 6310 includes, withoutlimitation, a kernel definition for an exemplary kernel “MatAdd” and amain function. In at least one embodiment, main function is host codethat executes on a host and includes, without limitation, a kernel callthat causes kernel MatAdd to execute on a device. In at least oneembodiment and as shown, kernel MatAdd adds two matrices A and B of sizeN×N, where N is a positive integer, and stores the result in a matrix C.In at least one embodiment, main function defines a threadsPerBlockvariable as 16 by 16 and a numBlocks variable as N/16 by N/16. In atleast one embodiment, main function then specifies kernel call“MatAdd<<<numBlocks, threadsPerBlock>>>(A, B, C);”. In at least oneembodiment and as per CUDA kernel launch syntax 6410, kernel MatAdd isexecuted using a grid of thread blocks having a dimension N/16 by N/16,where each thread block has a dimension of 16 by 16. In at least oneembodiment, each thread block includes 256 threads, a grid is createdwith enough blocks to have one thread per matrix element, and eachthread in such a grid executes kernel MatAdd to perform one pair-wiseaddition.

In at least one embodiment, while translating CUDA source code 6310 toHIP source code 6330, CUDA to HIP translation tool 6320 translates eachkernel call in CUDA source code 6310 from CUDA kernel launch syntax 6410to a HIP kernel launch syntax 6420 and converts any number of other CUDAcalls in source code 6310 to any number of other functionally similarHIP calls. In at least one embodiment, HIP kernel launch syntax 6420 isspecified as “hipLaunchKernelGGL(KernelName,GridSize, BlockSize,SharedMemory Size, Stream, KernelArguments);”. In at least oneembodiment, each of KernelName, GridSize, BlockSize, ShareMemorySize,Stream, and KernelArguments has the same meaning in HIP kernel launchsyntax 6420 as in CUDA kernel launch syntax 6410 (described previouslyherein). In at least one embodiment, arguments SharedMemorySize andStream are required in HIP kernel launch syntax 6420 and are optional inCUDA kernel launch syntax 6410.

In at least one embodiment, a portion of HIP source code 6330 depictedin FIG. 64 is identical to a portion of CUDA source code 6310 depictedin FIG. 64 except for a kernel call that causes kernel MatAdd to executeon a device. In at least one embodiment, kernel MatAdd is defined in HIPsource code 6330 with the same “_global_” declaration specifier withwhich kernel MatAdd is defined in CUDA source code 6310. In at least oneembodiment, a kernel call in HIP source code 6330 is“hipLaunchKernelGGL(MatAdd, numBlocks, threadsPerBlock, 0, 0, A, B,C);”, while a corresponding kernel call in CUDA source code 6310 is“MatAdd<<<numBlocks, threadsPerBlock>>>(A, B, C);”.

In at least one embodiment, at least one component shown or describedwith respect to FIG. 64 is used to implement techniques and/or functionsdescribed in connection with FIGS. 1-35 . In at least one embodiment, atleast one of CUDA Source Code 6410, CUDA to HIP Translation Tool 6420,or HIP Source Code 6430 is used to perform an application programminginterface to indicate two or more blocks of threads to be scheduled inparallel. In at least one embodiment, at least one of CUDA Source Code6410, CUDA to HIP Translation Tool 6420, or HIP Source Code 6430 is usedto perform an application programming interface to determine which oftwo or more blocks of threads to be scheduled in parallel. In at leastone embodiment, at least one of CUDA Source Code 6410, CUDA to HIPTranslation Tool 6420, or HIP Source Code 6430 is used to perform anapplication programming interface comprising one or more parameters tocause a scheduling policy of one or more blocks of one or more threadsto be performed. In at least one embodiment, at least one of CUDA SourceCode 6410, CUDA to HIP Translation Tool 6420, or HIP Source Code 6430 isused to perform an application programming interface comprising one ormore parameters to indicate a scheduling policy of one or more blocks ofone or more threads. In at least one embodiment, at least one of CUDASource Code 6410, CUDA to HIP Translation Tool 6420, or HIP Source Code6430 is used to perform an application programming interface to indicatea maximum number of blocks of threads capable of being scheduled inparallel. In at least one embodiment, at least one of CUDA Source Code6410, CUDA to HIP Translation Tool 6420, or HIP Source Code 6430 is usedto perform an application programming interface comprising one or moreparameters to indicate one or more attributes of one or more groups ofblocks of one or more threads. In at least one embodiment, at least oneof CUDA Source Code 6410, CUDA to HIP Translation Tool 6420, or HIPSource Code 6430 is used to perform an application programming interfaceto indicate a maximum number of blocks of threads to be scheduled inparallel. In at least one embodiment, at least one of CUDA Source Code6410, CUDA to HIP Translation Tool 6420, or HIP Source Code 6430 is usedto perform an application programming interface to cause a kernel to begenerated to cause two or more blocks of two or more threads to bescheduled in parallel. In at least one embodiment, at least one of CUDASource Code 6410, CUDA to HIP Translation Tool 6420, or HIP Source Code6430 is used to perform an application programming interface comprisingone or more parameters to indicate one or more limitations of one ormore attributes of one or more groups of blocks of one or more threads.In at least one embodiment, at least one of CUDA Source Code 6410, CUDAto HIP Translation Tool 6420, or HIP Source Code 6430 is used to performan application programming interface to indicate whether one or morethreads within two or more blocks of threads have performed a barrierinstruction. In at least one embodiment, at least one of CUDA SourceCode 6410, CUDA to HIP Translation Tool 6420, or HIP Source Code 6430 isused to perform an application programming interface to causeperformance of one or more threads within a group of blocks of threadsto stop at least until all threads within the group of blocks haveperformed a barrier instruction. In at least one embodiment, at leastone of CUDA Source Code 6410, CUDA to HIP Translation Tool 6420, or HIPSource Code 6430 is used to perform an application programming interfaceto indicate whether one or more threads within two or more blocks ofthreads have performed a barrier instruction and to cause performance ofone or more threads within the group of blocks of threads to stop atleast until all threads within the group of blocks have performed thebarrier instruction. In at least one embodiment, at least one of CUDASource Code 6410, CUDA to HIP Translation Tool 6420, or HIP Source Code6430 is used to perform an application programming interface to causememory to be shared between two or more groups of blocks of threads.

In at least one embodiment, at least one of CUDA Source Code 6410, CUDAto HIP Translation Tool 6420, or HIP Source Code 6430 is used to performat least one aspect described with respect to example computer system100, example diagram 200, example diagram 300, example diagram 400,example diagram 500, example process 600, example diagram 700, exampleapplication programming interface 800, example application programminginterface 900, example diagram 1000, example diagram 1100, exampleapplication programming interface 1200, example application programminginterface 1300, example computer system 1400, example applicationprogramming interface 1500, example diagram 1600, example applicationprogramming interface 1700, example computer system 1800, exampleapplication programming interface 1900, example computer system 2000,example application programming interface 2100, example diagram 2200,example diagram 2300, example diagram 2400, example diagram 2500,example application programming interface 2600, example diagram 2700,example diagram 2800, example diagram 2900, example applicationprogramming interface 3000, example application programming interface3100, example application programming interface 3200, example diagram3300, example application programming interface 3400, example softwarestack 3500, and/or other systems, methods, or operations describedherein.

FIG. 65 illustrates non-CUDA-enabled GPU 6392 of FIG. 63C in greaterdetail, in accordance with at least one embodiment. In at least oneembodiment, GPU 6392 is developed by AMD corporation of Santa Clara. Inat least one embodiment, GPU 6392 can be configured to perform computeoperations in a highly-parallel fashion. In at least one embodiment, GPU6392 is configured to execute graphics pipeline operations such as drawcommands, pixel operations, geometric computations, and other operationsassociated with rendering an image to a display. In at least oneembodiment, GPU 6392 is configured to execute operations unrelated tographics. In at least one embodiment, GPU 6392 is configured to executeboth operations related to graphics and operations unrelated tographics. In at least one embodiment, GPU 6392 can be configured toexecute device code included in HIP source code 6330.

In at least one embodiment, GPU 6392 includes, without limitation, anynumber of programmable processing units 6520, a command processor 6510,an L2 cache 6522, memory controllers 6570, DMA engines 6580(1), systemmemory controllers 6582, DMA engines 6580(2), and GPU controllers 6584.In at least one embodiment, each programmable processing unit 6520includes, without limitation, a workload manager 6530 and any number ofcompute units 6540. In at least one embodiment, command processor 6510reads commands from one or more command queues (not shown) anddistributes commands to workload managers 6530. In at least oneembodiment, for each programmable processing unit 6520, associatedworkload manager 6530 distributes work to compute units 6540 included inprogrammable processing unit 6520. In at least one embodiment, eachcompute unit 6540 may execute any number of thread blocks, but eachthread block executes on a single compute unit 6540. In at least oneembodiment, a workgroup is a thread block.

In at least one embodiment, each compute unit 6540 includes, withoutlimitation, any number of SIMD units 6550 and a shared memory 6560. Inat least one embodiment, each SIMD unit 6550 implements a SIMDarchitecture and is configured to perform operations in parallel. In atleast one embodiment, each SIMD unit 6550 includes, without limitation,a vector ALU 6552 and a vector register file 6554. In at least oneembodiment, each SIMD unit 6550 executes a different warp. In at leastone embodiment, a warp is a group of threads (e.g., 16 threads), whereeach thread in the warp belongs to a single thread block and isconfigured to process a different set of data based on a single set ofinstructions. In at least one embodiment, predication can be used todisable one or more threads in a warp. In at least one embodiment, alane is a thread. In at least one embodiment, a work item is a thread.In at least one embodiment, a wavefront is a warp. In at least oneembodiment, different wavefronts in a thread block may synchronizetogether and communicate via shared memory 6560.

In at least one embodiment, programmable processing units 6520 arereferred to as “shader engines.” In at least one embodiment, eachprogrammable processing unit 6520 includes, without limitation, anyamount of dedicated graphics hardware in addition to compute units 6540.In at least one embodiment, each programmable processing unit 6520includes, without limitation, any number (including zero) of geometryprocessors, any number (including zero) of rasterizers, any number(including zero) of render back ends, workload manager 6530, and anynumber of compute units 6540.

In at least one embodiment, compute units 6540 share L2 cache 6522. Inat least one embodiment, L2 cache 6522 is partitioned. In at least oneembodiment, a GPU memory 6590 is accessible by all compute units 6540 inGPU 6392. In at least one embodiment, memory controllers 6570 and systemmemory controllers 6582 facilitate data transfers between GPU 6392 and ahost, and DMA engines 6580(1) enable asynchronous memory transfersbetween GPU 6392 and such a host. In at least one embodiment, memorycontrollers 6570 and GPU controllers 6584 facilitate data transfersbetween GPU 6392 and other GPUs 6392, and DMA engines 6580(2) enableasynchronous memory transfers between GPU 6392 and other GPUs 6392.

In at least one embodiment, GPU 6392 includes, without limitation, anyamount and type of system interconnect that facilitates data and controltransmissions across any number and type of directly or indirectlylinked components that may be internal or external to GPU 6392. In atleast one embodiment, GPU 6392 includes, without limitation, any numberand type of I/O interfaces (e.g., PCIe) that are coupled to any numberand type of peripheral devices. In at least one embodiment, GPU 6392 mayinclude, without limitation, any number (including zero) of displayengines and any number (including zero) of multimedia engines. In atleast one embodiment, GPU 6392 implements a memory subsystem thatincludes, without limitation, any amount and type of memory controllers(e.g., memory controllers 6570 and system memory controllers 6582) andmemory devices (e.g., shared memories 6560) that may be dedicated to onecomponent or shared among multiple components. In at least oneembodiment, GPU 6392 implements a cache subsystem that includes, withoutlimitation, one or more cache memories (e.g., L2 cache 6522) that mayeach be private to or shared between any number of components (e.g.,SIMD units 6550, compute units 6540, and programmable processing units6520).

In at least one embodiment, at least one component shown or describedwith respect to FIG. 65 is used to implement techniques and/or functionsdescribed in connection with FIGS. 1-35 . In at least one embodiment, atleast one component shown or described with respect to FIG. is used toperform an application programming interface to indicate two or moreblocks of threads to be scheduled in parallel. In at least oneembodiment, at least one component shown or described with respect toFIG. 65 is used to perform an application programming interface todetermine which of two or more blocks of threads to be scheduled inparallel. In at least one embodiment, at least one component shown ordescribed with respect to FIG. 65 is used to perform an applicationprogramming interface comprising one or more parameters to cause ascheduling policy of one or more blocks of one or more threads to beperformed. In at least one embodiment, at least one component shown ordescribed with respect to FIG. 65 is used to perform an applicationprogramming interface comprising one or more parameters to indicate ascheduling policy of one or more blocks of one or more threads. In atleast one embodiment, at least one component shown or described withrespect to FIG. 65 is used to perform an application programminginterface to indicate a maximum number of blocks of threads capable ofbeing scheduled in parallel. In at least one embodiment, at least onecomponent shown or described with respect to FIG. 65 is used to performan application programming interface comprising one or more parametersto indicate one or more attributes of one or more groups of blocks ofone or more threads. In at least one embodiment, at least one componentshown or described with respect to FIG. 65 is used to perform anapplication programming interface to indicate a maximum number of blocksof threads to be scheduled in parallel. In at least one embodiment, atleast one component shown or described with respect to FIG. 65 is usedto perform an application programming interface to cause a kernel to begenerated to cause two or more blocks of two or more threads to bescheduled in parallel. In at least one embodiment, at least onecomponent shown or described with respect to FIG. 65 is used to performan application programming interface comprising one or more parametersto indicate one or more limitations of one or more attributes of one ormore groups of blocks of one or more threads. In at least oneembodiment, at least one component shown or described with respect toFIG. 65 is used to perform an application programming interface toindicate whether one or more threads within two or more blocks ofthreads have performed a barrier instruction. In at least oneembodiment, at least one component shown or described with respect toFIG. 65 is used to perform an application programming interface to causeperformance of one or more threads within a group of blocks of threadsto stop at least until all threads within the group of blocks haveperformed a barrier instruction. In at least one embodiment, at leastone component shown or described with respect to FIG. 65 is used toperform an application programming interface to indicate whether one ormore threads within two or more blocks of threads have performed abarrier instruction and to cause performance of one or more threadswithin the group of blocks of threads to stop at least until all threadswithin the group of blocks have performed the barrier instruction. In atleast one embodiment, at least one component shown or described withrespect to FIG. 65 is used to perform an application programminginterface to cause memory to be shared between two or more groups ofblocks of threads.

In at least one embodiment, at least one component shown or describedwith respect to FIG. 65 is used to perform at least one aspect describedwith respect to example computer system 100, example diagram 200,example diagram 300, example diagram 400, example diagram 500, exampleprocess 600, example diagram 700, example application programminginterface 800, example application programming interface 900, examplediagram 1000, example diagram 1100, example application programminginterface 1200, example application programming interface 1300, examplecomputer system 1400, example application programming interface 1500,example diagram 1600, example application programming interface 1700,example computer system 1800, example application programming interface1900, example computer system 2000, example application programminginterface 2100, example diagram 2200, example diagram 2300, examplediagram 2400, example diagram 2500, example application programminginterface 2600, example diagram 2700, example diagram 2800, examplediagram 2900, example application programming interface 3000, exampleapplication programming interface 3100, example application programminginterface 3200, example diagram 3300, example application programminginterface 3400, example software stack 3500, and/or other systems,methods, or operations described herein.

FIG. 66 illustrates how threads of an exemplary CUDA grid 6620 aremapped to different compute units 6540 of FIG. 65 , in accordance withat least one embodiment. In at least one embodiment and for explanatorypurposes only, grid 6620 has a GridSize of BX by BY by 1 and a BlockSizeof TX by TY by 1. In at least one embodiment, grid 6620 thereforeincludes, without limitation, (BX*BY) thread blocks 6630 and each threadblock 6630 includes, without limitation, (TX*TY) threads 6640. Threads6640 are depicted in FIG. 66 as squiggly arrows.

In at least one embodiment, grid 6620 is mapped to programmableprocessing unit 6520(1) that includes, without limitation, compute units6540(1)-6540(C). In at least one embodiment and as shown, (BJ*BY) threadblocks 6630 are mapped to compute unit 6540(1), and the remaining threadblocks 6630 are mapped to compute unit 6540(2). In at least oneembodiment, each thread block 6630 may include, without limitation, anynumber of warps, and each warp is mapped to a different SIMD unit 6550of FIG. 65 .

In at least one embodiment, warps in a given thread block 6630 maysynchronize together and communicate through shared memory 6560 includedin associated compute unit 6540. For example and in at least oneembodiment, warps in thread block 6630(BJ,1) can synchronize togetherand communicate through shared memory 6560(1). For example and in atleast one embodiment, warps in thread block 6630(BJ+1,1) can synchronizetogether and communicate through shared memory 6560(2).

In at least one embodiment, at least one component shown or describedwith respect to FIG. 66 is used to implement techniques and/or functionsdescribed in connection with FIGS. 1-35 . In at least one embodiment, atleast one thread of exemplary CUDA grid 6620 is used to perform anapplication programming interface to indicate two or more blocks ofthreads to be scheduled in parallel. In at least one embodiment, atleast one thread of exemplary CUDA grid 6620 is used to perform anapplication programming interface to determine which of two or moreblocks of threads to be scheduled in parallel. In at least oneembodiment, at least one thread of exemplary CUDA grid 6620 is used toperform an application programming interface comprising one or moreparameters to cause a scheduling policy of one or more blocks of one ormore threads to be performed. In at least one embodiment, at least onethread of exemplary CUDA grid 6620 is used to perform an applicationprogramming interface comprising one or more parameters to indicate ascheduling policy of one or more blocks of one or more threads. In atleast one embodiment, at least one thread of exemplary CUDA grid 6620 isused to perform an application programming interface to indicate amaximum number of blocks of threads capable of being scheduled inparallel. In at least one embodiment, at least one thread of exemplaryCUDA grid 6620 is used to perform an application programming interfacecomprising one or more parameters to indicate one or more attributes ofone or more groups of blocks of one or more threads. In at least oneembodiment, at least one thread of exemplary CUDA grid 6620 is used toperform an application programming interface to indicate a maximumnumber of blocks of threads to be scheduled in parallel. In at least oneembodiment, at least one thread of exemplary CUDA grid 6620 is used toperform an application programming interface to cause a kernel to begenerated to cause two or more blocks of two or more threads to bescheduled in parallel. In at least one embodiment, at least one threadof exemplary CUDA grid 6620 is used to perform an applicationprogramming interface comprising one or more parameters to indicate oneor more limitations of one or more attributes of one or more groups ofblocks of one or more threads. In at least one embodiment, at least onethread of exemplary CUDA grid 6620 is used to perform an applicationprogramming interface to indicate whether one or more threads within twoor more blocks of threads have performed a barrier instruction. In atleast one embodiment, at least one thread of exemplary CUDA grid 6620 isused to perform an application programming interface to causeperformance of one or more threads within a group of blocks of threadsto stop at least until all threads within the group of blocks haveperformed a barrier instruction. In at least one embodiment, at leastone thread of exemplary CUDA grid 6620 is used to perform an applicationprogramming interface to indicate whether one or more threads within twoor more blocks of threads have performed a barrier instruction and tocause performance of one or more threads within the group of blocks ofthreads to stop at least until all threads within the group of blockshave performed the barrier instruction. In at least one embodiment, atleast one thread of exemplary CUDA grid 6620 is used to perform anapplication programming interface to cause memory to be shared betweentwo or more groups of blocks of threads.

In at least one embodiment, at least one thread of exemplary CUDA grid6620 is used to perform at least one aspect described with respect toexample computer system 100, example diagram 200, example diagram 300,example diagram 400, example diagram 500, example process 600, examplediagram 700, example application programming interface 800, exampleapplication programming interface 900, example diagram 1000, examplediagram 1100, example application programming interface 1200, exampleapplication programming interface 1300, example computer system 1400,example application programming interface 1500, example diagram 1600,example application programming interface 1700, example computer system1800, example application programming interface 1900, example computersystem 2000, example application programming interface 2100, examplediagram 2200, example diagram 2300, example diagram 2400, examplediagram 2500, example application programming interface 2600, examplediagram 2700, example diagram 2800, example diagram 2900, exampleapplication programming interface 3000, example application programminginterface 3100, example application programming interface 3200, examplediagram 3300, example application programming interface 3400, examplesoftware stack 3500, and/or other systems, methods, or operationsdescribed herein.

FIG. 67 illustrates how to migrate existing CUDA code to Data ParallelC++ code, in accordance with at least one embodiment. Data Parallel C++(DPC++) may refer to an open, standards-based alternative tosingle-architecture proprietary languages that allows developers toreuse code across hardware targets (CPUs and accelerators such as GPUsand FPGAs) and also perform custom tuning for a specific accelerator.DPC++ use similar and/or identical C and C++ constructs in accordancewith ISO C++ which developers may be familiar with. DPC++ incorporatesstandard SYCL from The Khronos Group to support data parallelism andheterogeneous programming. SYCL refers to a cross-platform abstractionlayer that builds on underlying concepts, portability and efficiency ofOpenCL that enables code for heterogeneous processors to be written in a“single-source” style using standard C++. SYCL may enable single sourcedevelopment where C++ template functions can contain both host anddevice code to construct complex algorithms that use OpenCLacceleration, and then re-use them throughout their source code ondifferent types of data.

In at least one embodiment, a DPC++ compiler is used to compile DPC++source code which can be deployed across diverse hardware targets. In atleast one embodiment, a DPC++ compiler is used to generate DPC++applications that can be deployed across diverse hardware targets and aDPC++ compatibility tool can be used to migrate CUDA applications to amultiplatform program in DPC++. In at least one embodiment, a DPC++ basetool kit includes a DPC++ compiler to deploy applications across diversehardware targets; a DPC++ library to increase productivity andperformance across CPUs, GPUs, and FPGAs; a DPC++ compatibility tool tomigrate CUDA applications to multi-platform applications; and anysuitable combination thereof.

In at least one embodiment, a DPC++ programming model is utilized tosimply one or more aspects relating to programming CPUs and acceleratorsby using modern C++ features to express parallelism with a programminglanguage called Data Parallel C++. DPC++ programming language may beutilized to code reuse for hosts (e.g., a CPU) and accelerators (e.g., aGPU or FPGA) using a single source language, with execution and memorydependencies being clearly communicated. Mappings within DPC++ code canbe used to transition an application to run on a hardware or set ofhardware devices that best accelerates a workload. A host may beavailable to simplify development and debugging of device code, even onplatforms that do not have an accelerator available.

In at least one embodiment, CUDA source code 6700 is provided as aninput to a DPC++ compatibility tool 6702 to generate human readableDPC++ 6704. In at least one embodiment, human readable DPC++ 6704includes inline comments generated by DPC++ compatibility tool 6702 thatguides a developer on how and/or where to modify DPC++ code to completecoding and tuning to desired performance 6706, thereby generating DPC++source code 6708.

In at least one embodiment, CUDA source code 6700 is or includes acollection of human-readable source code in a CUDA programming language.In at least one embodiment, CUDA source code 6700 is human-readablesource code in a CUDA programming language. In at least one embodiment,a CUDA programming language is an extension of the C++ programminglanguage that includes, without limitation, mechanisms to define devicecode and distinguish between device code and host code. In at least oneembodiment, device code is source code that, after compilation, isexecutable on a device (e.g., GPU or FPGA) and may include or moreparallelizable workflows that can be executed on one or more processorcores of a device. In at least one embodiment, a device may be aprocessor that is optimized for parallel instruction processing, such asCUDA-enabled GPU, GPU, or another GPGPU, etc. In at least oneembodiment, host code is source code that, after compilation, isexecutable on a host. In least one embodiment, some or all of host codeand device code can be executed in parallel across a CPU and GPU/FPGA.In at least one embodiment, a host is a processor that is optimized forsequential instruction processing, such as CPU. CUDA source code 6700described in connection with FIG. 67 may be in accordance with thosediscussed elsewhere in this document.

In at least one embodiment, DPC++ compatibility tool 6702 refers to anexecutable tool, program, application, or any other suitable type oftool that is used to facilitate migration of CUDA source code 6700 toDPC++ source code 6708. In at least one embodiment, DPC++ compatibilitytool 6702 is a command-line-based code migration tool available as partof a DPC++ tool kit that is used to port existing CUDA sources to DPC++.In at least one embodiment, DPC++ compatibility tool 6702 converts someor all source code of a CUDA application from CUDA to DPC++ andgenerates a resulting file that is written at least partially in DPC++,referred to as human readable DPC++ 6704. In at least one embodiment,human readable DPC++ 6704 includes comments that are generated by DPC++compatibility tool 6702 to indicate where user intervention may benecessary. In at least one embodiment, user intervention is necessarywhen CUDA source code 6700 calls a CUDA API that has no analogous DPC++API; other examples where user intervention is required are discussedlater in greater detail.

In at least one embodiment, a workflow for migrating CUDA source code6700 (e.g., application or portion thereof) includes creating one ormore compilation database files; migrating CUDA to DPC++ using a DPC++compatibility tool 6702; completing migration and verifying correctness,thereby generating DPC++ source code 6708; and compiling DPC++ sourcecode 6708 with a DPC++ compiler to generate a DPC++ application. In atleast one embodiment, a compatibility tool provides a utility thatintercepts commands used when Makefile executes and stores them in acompilation database file. In at least one embodiment, a file is storedin JSON format. In at least one embodiment, an intercept-built commandconverts Makefile command to a DPC compatibility command.

In at least one embodiment, intercept-build is a utility script thatintercepts a build process to capture compilation options, macro defs,and include paths, and writes this data to a compilation database file.In at least one embodiment, a compilation database file is a JSON file.In at least one embodiment, DPC++ compatibility tool 6702 parses acompilation database and applies options when migrating input sources.In at least one embodiment, use of intercept-build is optional, buthighly recommended for Make or CMake based environments. In at least oneembodiment, a migration database includes commands, directories, andfiles: command may include necessary compilation flags; directory mayinclude paths to header files; file may include paths to CUDA files.

In at least one embodiment, DPC++ compatibility tool 6702 migrates CUDAcode (e.g., applications) written in CUDA to DPC++ by generating DPC++wherever possible. In at least one embodiment, DPC++ compatibility tool6702 is available as part of a tool kit. In at least one embodiment, aDPC++ tool kit includes an intercept-build tool. In at least oneembodiment, an intercept-built tool creates a compilation database thatcaptures compilation commands to migrate CUDA files. In at least oneembodiment, a compilation database generated by an intercept-built toolis used by DPC++ compatibility tool 6702 to migrate CUDA code to DPC++.In at least one embodiment, non-CUDA C++ code and files are migrated asis. In at least one embodiment, DPC++ compatibility tool 6702 generateshuman readable DPC++ 6704 which may be DPC++ code that, as generated byDPC++ compatibility tool 6702, cannot be compiled by DPC++ compiler andrequires additional plumbing for verifying portions of code that werenot migrated correctly, and may involve manual intervention, such as bya developer. In at least one embodiment, DPC++ compatibility tool 6702provides hints or tools embedded in code to help developers manuallymigrate additional code that could not be migrated automatically. In atleast one embodiment, migration is a one-time activity for a sourcefile, project, or application.

In at least one embodiment, DPC++ compatibility tool 67002 is able tosuccessfully migrate all portions of CUDA code to DPC++ and there maysimply be an optional step for manually verifying and tuning performanceof DPC++ source code that was generated. In at least one embodiment,DPC++ compatibility tool 6702 directly generates DPC++ source code 6708which is compiled by a DPC++ compiler without requiring or utilizinghuman intervention to modify DPC++ code generated by DPC++ compatibilitytool 6702. In at least one embodiment, DPC++ compatibility toolgenerates compile-able DPC++ code which can be optionally tuned by adeveloper for performance, readability, maintainability, other variousconsiderations; or any combination thereof.

In at least one embodiment, one or more CUDA source files are migratedto DPC++ source files at least partially using DPC++ compatibility tool6702. In at least one embodiment, CUDA source code includes one or moreheader files which may include CUDA header files. In at least oneembodiment, a CUDA source file includes a <cuda.h> header file and a<stdio.h> header file which can be used to print text. In at least oneembodiment, a portion of a vector addition kernel CUDA source file maybe written as or related to:

#include <cuda.h> #include <stdio.h> #define VECTOR_SIZE 256 [ ]global_(——) void VectorAddKernel(float* A, float* B, float* C) { A[threadIdx.x] = threadIdx.x + 1.0f;  B[threadIdx.x] = threadIdx.x +1.0f;  C[threadIdx.x] = A[threadIdx.x] + B[threadIdx.x]; } int main( ) { float *d_A, *d_B, *d_C;  cudaMalloc(&d_A, VECTOR_SIZE*sizeof(float)); cudaMalloc(&d_B, VECTOR_SIZE*sizeof(float));  cudaMalloc(&d_C,VECTOR_SIZE*sizeof(float));  VectorAddKernel<<<1, VECTOR_SIZE>>>(d_A,d_B, d_C);  float Result[VECTOR_SIZE] = { };  cudaMemcpy(Result, d_C,VECTOR_SIZE*sizeof(float), cudaMemcpyDeviceToHost);  cudaFree(d_A); cudaFree(d_B);  cudaFree(d_C);  for (int i=0; i<VECTOR_SIZE; i++ {   if(i % 16 == 0) {    printf(“\n”);   }   printf(“%f ”, Result[i]);  } return 0; }

In at least one embodiment and in connection with CUDA source filepresented above, DPC++ compatibility tool 6702 parses a CUDA source codeand replaces header files with appropriate DPC++ and SYCL header files.In at least one embodiment, DPC++ header files includes helperdeclarations. In CUDA, there is a concept of a thread ID andcorrespondingly, in DPC++ or SYCL, for each element there is a localidentifier.

In at least one embodiment and in connection with CUDA source filepresented above, there are two vectors A and B which are initialized anda vector addition result is put into vector C as part ofVectorAddKernel( ). In at least one embodiment, DPC++ compatibility tool6702 converts CUDA thread IDs used to index work elements to SYCLstandard addressing for work elements via a local ID as part ofmigrating CUDA code to DPC++ code. In at least one embodiment, DPC++code generated by DPC++ compatibility tool 6702 can be optimized—forexample, by reducing dimensionality of an nd_item, thereby increasingmemory and/or processor utilization.

In at least one embodiment and in connection with CUDA source filepresented above, memory allocation is migrated. In at least oneembodiment, cudaMalloc( ) is migrated to a unified shared memory SYCLcall malloc_device( ) to which a device and context is passed, relyingon SYCL concepts such as platform, device, context, and queue. In atleast one embodiment, a SYCL platform can have multiple devices (e.g.,host and GPU devices); a device may have multiple queues to which jobscan be submitted; each device may have a context; and a context may havemultiple devices and manage shared memory objects.

In at least one embodiment and in connection with CUDA source filepresented above, a main( ) function invokes or calls VectorAddKernel( )to add two vectors A and B together and store result in vector C. In atleast one embodiment, CUDA code to invoke VectorAddKernel( ) is replacedby DPC++ code to submit a kernel to a command queue for execution. In atleast one embodiment, a command group handler cgh passes data,synchronization, and computation that is submitted to the queue,parallel_for is called for a number of global elements and a number ofwork items in that work group where VectorAddKernel( ) is called.

In at least one embodiment and in connection with CUDA source filepresented above, CUDA calls to copy device memory and then free memoryfor vectors A, B, and C are migrated to corresponding DPC++ calls. In atleast one embodiment, C++ code (e.g., standard ISO C++ code for printinga vector of floating point variables) is migrated as is, without beingmodified by DPC++ compatibility tool 6702. In at least one embodiment,DPC++ compatibility tool 6702 modify CUDA APIs for memory setup and/orhost calls to execute kernel on the acceleration device. In at least oneembodiment and in connection with CUDA source file presented above, acorresponding human readable DPC++ 6704 (e.g., which can be compiled) iswritten as or related to:

#include <CL/sycl.hpp> #include <dpct/dpct.hpp> #define VECTOR_SIZE 256void VectorAddKernel(float* A, float* B, float* C,      sycl::nd_item<3>item_ct1) {  A[item_ct1.get_local_id(2)] = item_ct1.get_local_id(2) +1.0f;  B[item_ct1.get_local_id(2)] = item_ct1.get_local_id(2) + 1.0f; C[item_ct1.get_local_id(2)] =    A[item_ct1.get_local_id(2)] +B[item_ct1.get_local_id(2)]; } int main( ) {  float *d_A, *d_B, *d_C; d_A = (float *)sycl::malloc_device(VECTOR_SIZE * sizeof(float),  dpct::get_current_device( ),   dpct::get_default_context( ));  d_B =(float *)sycl::malloc_device(VECTOR_SIZE * sizeof(float),  dpct::get_current_device( ),   dpct::get_default_context( ));  d_C =(float *)sycl::malloc_device(VECTOR_SIZE * sizeof(float),  dpct::get_current_device( ),   dpct::get_default_context( )); dpct::get_default_queue_wait( ).submit([&](sycl::handler &cgh) {  cgh.parallel_for(    sycl::nd_range<3>(sycl::range<3>(1, 1, 1) *      sycl::range<3>(1, 1, VECTOR_SIZE) *       sycl::range<3>(1, 1,VECTOR_SIZE)),    [=](sycl::nd_items<3> item_ct1) {    VectorAddKernel(d_A, d_B, d_C, item_ct1);    });  });  floatResult[VECTOR_SIZE] = { };  dpct::get_default_queue_wait( )  .memcpy(Result, d_C, VECTOR_SIZE * sizeof(float))   .wait( ); sycl::free(d_A, dpct::get_default_context( ));  sycl::free(d_B,dpct::get_default_context( ));  sycl::free(d_C,dpct::get_default_context( ));  for (int i=0; i<VECTOR_SIZE; i++ {   if(i % 16 == 0) {     printf(“\n”);   }   printf(“%f ”, Result[i]);  } return 0; }

In at least one embodiment, human readable DPC++ 6704 refers to outputgenerated by DPC++ compatibility tool 6702 and may be optimized in onemanner or another. In at least one embodiment, human readable DPC++ 6704generated by DPC++ compatibility tool 6702 can be manually edited by adeveloper after migration to make it more maintainable, performance, orother considerations. In at least one embodiment, DPC++ code generatedby DPC++ compatibility tool 67002 such as DPC++ disclosed can beoptimized by removing repeat calls to get current device( ) and/orget_default_context( ) for each malloc_device( ) call. In at least oneembodiment, DPC++ code generated above uses a 3 dimensional nd_rangewhich can be refactored to use only a single dimension, thereby reducingmemory usage. In at least one embodiment, a developer can manually editDPC++ code generated by DPC++ compatibility tool 6702 replace uses ofunified shared memory with accessors. In at least one embodiment, DPC++compatibility tool 6702 has an option to change how it migrates CUDAcode to DPC++ code. In at least one embodiment, DPC++ compatibility tool6702 is verbose because it is using a general template to migrate CUDAcode to DPC++ code that works for a large number of cases.

In at least one embodiment, a CUDA to DPC++ migration workflow includessteps to: prepare for migration using intercept-build script; performmigration of CUDA projects to DPC++ using DPC++ compatibility tool 6702;review and edit migrated source files manually for completion andcorrectness; and compile final DPC++ code to generate a DPC++application. In at least one embodiment, manual review of DPC++ sourcecode may be required in one or more scenarios including but not limitedto: migrated API does not return error code (CUDA code can return anerror code which can then be consumed by the application but SYCL usesexceptions to report errors, and therefore does not use error codes tosurface errors); CUDA compute capability dependent logic is notsupported by DPC++; statement could not be removed. In at least oneembodiment, scenarios in which DPC++ code requires manual interventionmay include, without limitation: error code logic replaced with (*,0)code or commented out; equivalent DPC++ API not available; CUDA computecapability-dependent logic; hardware-dependent API (clock( ); missingfeatures unsupported API; execution time measurement logic; handlingbuilt-in vector type conflicts; migration of cuBLAS API; and more.

In at least one embodiment, one or more techniques described hereinutilize a oneAPI programming model. In at least one embodiment, a oneAPIprogramming model refers to a programming model for interacting withvarious compute accelerator architectures. In at least one embodiment,oneAPI refers to an application programming interface (API) designed tointeract with various compute accelerator architectures. In at least oneembodiment, a oneAPI programming model utilizes a DPC++ programminglanguage. In at least one embodiment, a DPC++ programming languagerefers to a high-level language for data parallel programmingproductivity. In at least one embodiment, a DPC++ programming languageis based at least in part on C and/or C++ programming languages. In atleast one embodiment, a oneAPI programming model is a programming modelsuch as those developed by Intel Corporation of Santa Clara, CA.

In at least one embodiment, oneAPI and/or oneAPI programming model isutilized to interact with various accelerator, GPU, processor, and/orvariations thereof, architectures. In at least one embodiment, oneAPIincludes a set of libraries that implement various functionalities. Inat least one embodiment, oneAPI includes at least a oneAPI DPC++library, a oneAPI math kernel library, a oneAPI data analytics library,a oneAPI deep neural network library, a oneAPI collective communicationslibrary, a oneAPI threading building blocks library, a oneAPI videoprocessing library, and/or variations thereof.

In at least one embodiment, a oneAPI DPC++ library, also referred to asoneDPL, is a library that implements algorithms and functions toaccelerate DPC++ kernel programming. In at least one embodiment, oneDPLimplements one or more standard template library (STL) functions. In atleast one embodiment, oneDPL implements one or more parallel STLfunctions. In at least one embodiment, oneDPL provides a set of libraryclasses and functions such as parallel algorithms, iterators, functionobject classes, range-based API, and/or variations thereof. In at leastone embodiment, oneDPL implements one or more classes and/or functionsof a C++ standard library. In at least one embodiment, oneDPL implementsone or more random number generator functions.

In at least one embodiment, a oneAPI math kernel library, also referredto as oneMKL, is a library that implements various optimized andparallelized routines for various mathematical functions and/oroperations. In at least one embodiment, oneMKL implements one or morebasic linear algebra subprograms (BLAS) and/or linear algebra package(LAPACK) dense linear algebra routines. In at least one embodiment,oneMKL implements one or more sparse BLAS linear algebra routines. In atleast one embodiment, oneMKL implements one or more random numbergenerators (RNGs). In at least one embodiment, oneMKL implements one ormore vector mathematics (VM) routines for mathematical operations onvectors. In at least one embodiment, oneMKL implements one or more FastFourier Transform (FFT) functions.

In at least one embodiment, a oneAPI data analytics library, alsoreferred to as oneDAL, is a library that implements various dataanalysis applications and distributed computations. In at least oneembodiment, oneDAL implements various algorithms for preprocessing,transformation, analysis, modeling, validation, and decision making fordata analytics, in batch, online, and distributed processing modes ofcomputation. In at least one embodiment, oneDAL implements various C++and/or Java APIs and various connectors to one or more data sources. Inat least one embodiment, oneDAL implements DPC++ API extensions to atraditional C++ interface and enables GPU usage for various algorithms.

In at least one embodiment, a oneAPI deep neural network library, alsoreferred to as oneDNN, is a library that implements various deeplearning functions. In at least one embodiment, oneDNN implementsvarious neural network, machine learning, and deep learning functions,algorithms, and/or variations thereof.

In at least one embodiment, a oneAPI collective communications library,also referred to as oneCCL, is a library that implements variousapplications for deep learning and machine learning workloads. In atleast one embodiment, oneCCL is built upon lower-level communicationmiddleware, such as message passing interface (MPI) and libfabrics. Inat least one embodiment, oneCCL enables a set of deep learning specificoptimizations, such as prioritization, persistent operations, out oforder executions, and/or variations thereof. In at least one embodiment,oneCCL implements various CPU and GPU functions.

In at least one embodiment, a oneAPI threading building blocks library,also referred to as oneTBB, is a library that implements variousparallelized processes for various applications. In at least oneembodiment, oneTBB is utilized for task-based, shared parallelprogramming on a host. In at least one embodiment, oneTBB implementsgeneric parallel algorithms. In at least one embodiment, oneTBBimplements concurrent containers. In at least one embodiment, oneTBBimplements a scalable memory allocator. In at least one embodiment,oneTBB implements a work-stealing task scheduler. In at least oneembodiment, oneTBB implements low-level synchronization primitives. Inat least one embodiment, oneTBB is compiler-independent and usable onvarious processors, such as GPUs, PPUs, CPUs, and/or variations thereof.

In at least one embodiment, a oneAPI video processing library, alsoreferred to as oneVPL, is a library that is utilized for acceleratingvideo processing in one or more applications. In at least oneembodiment, oneVPL implements various video decoding, encoding, andprocessing functions. In at least one embodiment, oneVPL implementsvarious functions for media pipelines on CPUs, GPUs, and otheraccelerators. In at least one embodiment, oneVPL implements devicediscovery and selection in media centric and video analytics workloads.In at least one embodiment, oneVPL implements API primitives forzero-copy buffer sharing.

In at least one embodiment, a oneAPI programming model utilizes a DPC++programming language. In at least one embodiment, a DPC++ programminglanguage is a programming language that includes, without limitation,functionally similar versions of CUDA mechanisms to define device codeand distinguish between device code and host code. In at least oneembodiment, a DPC++ programming language may include a subset offunctionality of a CUDA programming language. In at least oneembodiment, one or more CUDA programming model operations are performedusing a oneAPI programming model using a DPC++ programming language.

In at least one embodiment, at least one component shown or describedwith respect to FIG. 67 is used to implement techniques and/or functionsdescribed in connection with FIGS. 1-35 . In at least one embodiment, atleast one component shown or described with respect to FIG. 67 is usedto perform an application programming interface to indicate two or moreblocks of threads to be scheduled in parallel. In at least oneembodiment, at least one component shown or described with respect toFIG. 67 is used to perform an application programming interface todetermine which of two or more blocks of threads to be scheduled inparallel. In at least one embodiment, at least one component shown ordescribed with respect to FIG. 67 is used to perform an applicationprogramming interface comprising one or more parameters to cause ascheduling policy of one or more blocks of one or more threads to beperformed. In at least one embodiment, at least one component shown ordescribed with respect to FIG. 67 is used to perform an applicationprogramming interface comprising one or more parameters to indicate ascheduling policy of one or more blocks of one or more threads. In atleast one embodiment, at least one component shown or described withrespect to FIG. 67 is used to perform an application programminginterface to indicate a maximum number of blocks of threads capable ofbeing scheduled in parallel. In at least one embodiment, at least onecomponent shown or described with respect to FIG. 67 is used to performan application programming interface comprising one or more parametersto indicate one or more attributes of one or more groups of blocks ofone or more threads. In at least one embodiment, at least one componentshown or described with respect to FIG. 67 is used to perform anapplication programming interface to indicate a maximum number of blocksof threads to be scheduled in parallel. In at least one embodiment, atleast one component shown or described with respect to FIG. 67 is usedto perform an application programming interface to cause a kernel to begenerated to cause two or more blocks of two or more threads to bescheduled in parallel. In at least one embodiment, at least onecomponent shown or described with respect to FIG. 67 is used to performan application programming interface comprising one or more parametersto indicate one or more limitations of one or more attributes of one ormore groups of blocks of one or more threads. In at least oneembodiment, at least one component shown or described with respect toFIG. 67 is used to perform an application programming interface toindicate whether one or more threads within two or more blocks ofthreads have performed a barrier instruction. In at least oneembodiment, at least one component shown or described with respect toFIG. 67 is used to perform an application programming interface to causeperformance of one or more threads within a group of blocks of threadsto stop at least until all threads within the group of blocks haveperformed a barrier instruction. In at least one embodiment, at leastone component shown or described with respect to FIG. 67 is used toperform an application programming interface to indicate whether one ormore threads within two or more blocks of threads have performed abarrier instruction and to cause performance of one or more threadswithin the group of blocks of threads to stop at least until all threadswithin the group of blocks have performed the barrier instruction. In atleast one embodiment, at least one component shown or described withrespect to FIG. 67 is used to perform an application programminginterface to cause memory to be shared between two or more groups ofblocks of threads.

In at least one embodiment at least one component shown or describedwith respect to FIG. 67 is used to perform at least one aspect describedwith respect to example computer system 100, example diagram 200,example diagram 300, example diagram 400, example diagram 500, exampleprocess 600, example diagram 700, example application programminginterface 800, example application programming interface 900, examplediagram 1000, example diagram 1100, example application programminginterface 1200, example application programming interface 1300, examplecomputer system 1400, example application programming interface 1500,example diagram 1600, example application programming interface 1700,example computer system 1800, example application programming interface1900, example computer system 2000, example application programminginterface 2100, example diagram 2200, example diagram 2300, examplediagram 2400, example diagram 2500, example application programminginterface 2600, example diagram 2700, example diagram 2800, examplediagram 2900, example application programming interface 3000, exampleapplication programming interface 3100, example application programminginterface 3200, example diagram 3300, example application programminginterface 3400, example software stack 3500, and/or other systems,methods, or operations described herein.

It should be noted that, while example embodiments described herein mayrelate to a CUDA programming model, techniques described herein can beutilized with any suitable programming model, such HIP, oneAPI (e.g.,using oneAPI-based programming to perform or implement a methoddisclosed herein), and/or variations thereof.

In at least one embodiment, one or more components of systems and/orprocessors disclosed above can communicate with one or more CPUs, ASICs,GPUs, FPGAs, or other hardware, circuitry, or integrated circuitcomponents that include, e.g., an upscaler or upsampler to upscale animage, an image blender or image blender component to blend, mix, or addimages together, a sampler to sample an image (e.g., as part of a DSP),a neural network circuit that is configured to perform an upscaler toupscale an image (e.g., from a low resolution image to a high resolutionimage), or other hardware to modify or generate an image, frame, orvideo to adjust its resolution, size, or pixels; one or more componentsof systems and/or processors disclosed above can use componentsdescribed in this disclosure to perform methods, operations, orinstructions that generate or modify an image.

At least one embodiment of the disclosure can be described in view ofthe following clauses:

-   -   1. A processor comprising:    -   one or more circuits to perform an application programming        interface (API) to indicate a maximum number of blocks of        threads capable of being scheduled in parallel.    -   2. The processor of clause 1, wherein the maximum number is of a        group of blocks, the group being of multiple groups of blocks of        threads of a software kernel.    -   3. The processor of clause 1 or 2, wherein the maximum number is        of a group of blocks of multiple groups of blocks of a grid of        blocks.    -   4. The processor of any of clauses 1-3, wherein the maximum        number of blocks is based, at least in part, on an architecture        of a graphics processing unit (GPU).    -   The processor of any of clauses 1-4, wherein the maximum number        of blocks is a limit of a number of allowable groups of blocks        of threads of a software kernel.    -   6. The processor of any of clauses 1-5, wherein the API is to        indicate the maximum number by returning the maximum number.    -   7. The processor of any of clauses 1-6, wherein the maximum        number is based, at least in part, on one or more properties of        another processor.    -   8. The processor of any of clauses 1-7, wherein the maximum        number is a limit on a number of partitions of blocks of threads        of a group of threads.    -   9. The processor of any of clauses 1-8, wherein the maximum        number is a limit on a number of blocks in a group of blocks,        the group of blocks being one of multiple groups of blocks of a        grid of blocks.    -   10. A computer-implemented method comprising:    -   performing an application programming interface (API) to        indicate a maximum number of blocks of threads capable of being        scheduled in parallel.    -   11. The computer-implemented method of clause 10, wherein the        maximum number is of a group of blocks, the group being of        multiple groups of blocks of threads of a software kernel.    -   12. The computer-implemented method of clause 10 or 11, wherein        the maximum number is of a group of blocks of multiple groups of        blocks of a grid of blocks.    -   13. The computer-implemented method of any of clauses 10-12,        wherein the API the maximum number of blocks is based, at least        in part, on an architecture of a graphics processing unit (GPU).    -   14. The computer-implemented method of any of clauses 10-13,        wherein the maximum number of blocks is a limit of a number of        allowable groups of blocks of threads of a software kernel.    -   15. The computer-implemented method of any of clauses 10-14,        wherein the API is to indicate the maximum number by returning        the maximum number.    -   16. The computer-implemented method of any of clauses 10-15,        wherein the maximum number is based, at least in part, on one or        more properties of a GPU.    -   17. The computer-implemented method of any of clauses 10-16,        wherein the maximum number is a limit on a number of partitions        of blocks of threads of a group of threads.    -   18. The computer-implemented method of any of clauses 10-17,        wherein the maximum number is a limit on a number of blocks in a        group of blocks, the group of blocks being one of multiple        groups of blocks of a grid of blocks.    -   19. A computer system comprising:    -   one or more processors and memory storing executable        instructions that, if performed by the one or more processors,        are to perform an application programming interface (API) to        indicate a maximum number of blocks of threads capable of being        scheduled in parallel.    -   20. The computer system of clause 19, wherein the maximum number        is of a group of blocks, the group being of multiple groups of        blocks of threads of a software kernel.    -   21. The computer system of clause 19 or 20, wherein the maximum        number is of a group of blocks of multiple groups of blocks of a        grid of blocks.    -   22. The computer system of any of clauses 19-21, wherein the API        the maximum number of blocks is based, at least in part, on an        architecture of a graphics processing unit (GPU).    -   23. The computer system of any of clauses 19-22, wherein the        maximum number of blocks is a limit of a number of allowable        groups of blocks of threads of a software kernel.    -   24. The computer system of any of clauses 19-23, wherein the API        is to indicate the maximum number by returning the maximum        number.    -   25. The computer system of any of clauses 19-24, wherein the        maximum number is based, at least in part, on one or more        properties of a processor of the one or more processors.    -   26. The computer system of any of clauses 19-25, wherein the        maximum number is a limit on a number of partitions of blocks of        threads of a group of threads.    -   27. The computer system of any of clauses 19-26, wherein the        maximum number is a limit on a number of blocks in a group of        blocks, the group of blocks being one of multiple groups of        blocks of a grid of blocks.    -   28. A machine-readable medium having stored thereon a set of        instructions, which if performed by one or more processors, are        to perform an application programming interface (API) to        indicate a maximum number of blocks of threads capable of being        scheduled in parallel.    -   29. The machine-readable medium of clause 28, wherein the        maximum number is of a group of blocks, the group being of        multiple groups of blocks of threads of a software kernel.    -   30. The machine-readable medium of clause 28 or 29, wherein the        maximum number is of a group of blocks of multiple groups of        blocks of a grid of blocks.    -   31. The machine-readable medium of any of clauses 28-30, wherein        the API the maximum number of blocks is based, at least in part,        on an architecture of a graphics processing unit (GPU).    -   32. The machine-readable medium of any of clauses 28-31, wherein        the maximum number of blocks is a limit of a number of allowable        groups of blocks of threads of a software kernel.    -   33. The machine-readable medium of any of clauses 28-32, wherein        the API is to indicate the maximum number by returning the        maximum number.    -   34. The machine-readable medium of any of clauses 28-33, wherein        the maximum number is based, at least in part, on one or more        properties of a processor of the one or more processors.    -   35. The machine-readable medium of any of clauses 28-34, wherein        the maximum number is a limit on a number of partitions of        blocks of threads of a group of threads.    -   36. The machine-readable medium of any of clauses 28-35, wherein        the maximum number is a limit on a number of blocks in a group        of blocks, the group of blocks being one of multiple groups of        blocks of a grid of blocks.

Other variations are within spirit of present disclosure. Thus, whiledisclosed techniques are susceptible to various modifications andalternative constructions, certain illustrated embodiments thereof areshown in drawings and have been described above in detail. It should beunderstood, however, that there is no intention to limit disclosure tospecific form or forms disclosed, but on contrary, intention is to coverall modifications, alternative constructions, and equivalents fallingwithin spirit and scope of disclosure, as defined in appended claims.

Use of terms “a” and “an” and “the” and similar referents in context ofdescribing disclosed embodiments (especially in context of followingclaims) are to be construed to cover both singular and plural, unlessotherwise indicated herein or clearly contradicted by context, and notas a definition of a term. Terms “comprising,” “having,” “including,”and “containing” are to be construed as open-ended terms (meaning“including, but not limited to,”) unless otherwise noted. term“connected,” when unmodified and referring to physical connections, isto be construed as partly or wholly contained within, attached to, orjoined together, even if there is something intervening. Recitation ofranges of values herein are merely intended to serve as a shorthandmethod of referring individually to each separate value falling withinrange, unless otherwise indicated herein and each separate value isincorporated into specification as if it were individually recitedherein. Use of term “set” (e.g., “a set of items”) or “subset” unlessotherwise noted or contradicted by context, is to be construed as anonempty collection comprising one or more members. Further, unlessotherwise noted or contradicted by context, term “subset” of acorresponding set does not necessarily denote a proper subset ofcorresponding set, but subset and corresponding set may be equal.

Conjunctive language, such as phrases of form “at least one of A, B, andC,” or “at least one of A, B and C,” unless specifically statedotherwise or otherwise clearly contradicted by context, is otherwiseunderstood with context as used in general to present that an item,term, etc., may be either A or B or C, or any nonempty subset of set ofA and B and C. For instance, in illustrative example of a set havingthree members, conjunctive phrases “at least one of A, B, and C” and “atleast one of A, B and C” refer to any of following sets: {A}, {B}, {C},{A, B}, {A, C}, {B, C}, {A, B, C}. Thus, such conjunctive language isnot generally intended to imply that certain embodiments require atleast one of A, at least one of B and at least one of C each to bepresent. In addition, unless otherwise noted or contradicted by context,term “plurality” indicates a state of being plural (e.g., “a pluralityof items” indicates multiple items). A number of items in a plurality isat least two, but can be more when so indicated either explicitly or bycontext. Further, unless stated otherwise or otherwise clear fromcontext, phrase “based on” means “based at least in part on” and not“based solely on.”

Operations of processes described herein can be performed in anysuitable order unless otherwise indicated herein or otherwise clearlycontradicted by context. In at least one embodiment, a process such asthose processes described herein (or variations and/or combinationsthereof) is performed under control of one or more computer systemsconfigured with executable instructions and is implemented as code(e.g., executable instructions, one or more computer programs or one ormore applications) executing collectively on one or more processors, byhardware or combinations thereof. In at least one embodiment, code isstored on a computer-readable storage medium, for example, in form of acomputer program comprising a plurality of instructions executable byone or more processors. In at least one embodiment, a computer-readablestorage medium is a non-transitory computer-readable storage medium thatexcludes transitory signals (e.g., a propagating transient electric orelectromagnetic transmission) but includes non-transitory data storagecircuitry (e.g., buffers, cache, and queues) within transceivers oftransitory signals. In at least one embodiment, code (e.g., executablecode or source code) is stored on a set of one or more non-transitorycomputer-readable storage media having stored thereon executableinstructions (or other memory to store executable instructions) that,when executed (e.g., as a result of being executed) by one or moreprocessors of a computer system, cause computer system to performoperations described herein. A set of non-transitory computer-readablestorage media, in at least one embodiment, comprises multiplenon-transitory computer-readable storage media and one or more ofindividual non-transitory storage media of multiple non-transitorycomputer-readable storage media lack all of code while multiplenon-transitory computer-readable storage media collectively store all ofcode. In at least one embodiment, executable instructions are executedsuch that different instructions are executed by differentprocessors—for example, a non-transitory computer-readable storagemedium store instructions and a main central processing unit (“CPU”)executes some of instructions while a graphics processing unit (“GPU”)executes other instructions. In at least one embodiment, differentcomponents of a computer system have separate processors and differentprocessors execute different subsets of instructions.

Accordingly, in at least one embodiment, computer systems are configuredto implement one or more services that singly or collectively performoperations of processes described herein and such computer systems areconfigured with applicable hardware and/or software that enableperformance of operations. Further, a computer system that implements atleast one embodiment of present disclosure is a single device and, inanother embodiment, is a distributed computer system comprising multipledevices that operate differently such that distributed computer systemperforms operations described herein and such that a single device doesnot perform all operations.

Use of any and all examples, or exemplary language (e.g., “such as”)provided herein, is intended merely to better illuminate embodiments ofdisclosure and does not pose a limitation on scope of disclosure unlessotherwise claimed. No language in specification should be construed asindicating any non-claimed element as essential to practice ofdisclosure.

All references, including publications, patent applications, andpatents, cited herein are hereby incorporated by reference to sameextent as if each reference were individually and specifically indicatedto be incorporated by reference and were set forth in its entiretyherein.

In description and claims, terms “coupled” and “connected,” along withtheir derivatives, may be used. It should be understood that these termsmay be not intended as synonyms for each other. Rather, in particularexamples, “connected” or “coupled” may be used to indicate that two ormore elements are in direct or indirect physical or electrical contactwith each other. “Coupled” may also mean that two or more elements arenot in direct contact with each other, but yet still co-operate orinteract with each other.

Unless specifically stated otherwise, it may be appreciated thatthroughout specification terms such as “processing,” “computing,”“calculating,” “determining,” or like, refer to action and/or processesof a computer or computing system, or similar electronic computingdevice, that manipulate and/or transform data represented as physical,such as electronic, quantities within computing system's registersand/or memories into other data similarly represented as physicalquantities within computing system's memories, registers or other suchinformation storage, transmission or display devices.

In a similar manner, term “processor” may refer to any device or portionof a device that processes electronic data from registers and/or memoryand transform that electronic data into other electronic data that maybe stored in registers and/or memory. As non-limiting examples,“processor” may be a CPU or a GPU. A “computing platform” may compriseone or more processors. As used herein, “software” processes mayinclude, for example, software and/or hardware entities that performwork over time, such as tasks, threads, and intelligent agents. Also,each process may refer to multiple processes, for carrying outinstructions in sequence or in parallel, continuously or intermittently.Terms “system” and “method” are used herein interchangeably insofar assystem may embody one or more methods and methods may be considered asystem.

In at least one embodiment, an arithmetic logic unit is a set ofcombinational logic circuitry that takes one or more inputs to produce aresult. In at least one embodiment, an arithmetic logic unit is used bya processor to implement mathematical operation such as addition,subtraction, or multiplication. In at least one embodiment, anarithmetic logic unit is used to implement logical operations such aslogical AND/OR or XOR. In at least one embodiment, an arithmetic logicunit is stateless, and made from physical switching components such assemiconductor transistors arranged to form logical gates. In at leastone embodiment, an arithmetic logic unit may operate internally as astateful logic circuit with an associated clock. In at least oneembodiment, an arithmetic logic unit may be constructed as anasynchronous logic circuit with an internal state not maintained in anassociated register set. In at least one embodiment, an arithmetic logicunit is used by a processor to combine operands stored in one or moreregisters of the processor and produce an output that can be stored bythe processor in another register or a memory location.

In at least one embodiment, as a result of processing an instructionretrieved by the processor, the processor presents one or more inputs oroperands to an arithmetic logic unit, causing the arithmetic logic unitto produce a result based at least in part on an instruction codeprovided to inputs of the arithmetic logic unit. In at least oneembodiment, the instruction codes provided by the processor to the ALUare based at least in part on the instruction executed by the processor.In at least one embodiment combinational logic in the ALU processes theinputs and produces an output which is placed on a bus within theprocessor. In at least one embodiment, the processor selects adestination register, memory location, output device, or output storagelocation on the output bus so that clocking the processor causes theresults produced by the ALU to be sent to the desired location.

In present document, references may be made to obtaining, acquiring,receiving, or inputting analog or digital data into a subsystem,computer system, or computer-implemented machine. Process of obtaining,acquiring, receiving, or inputting analog and digital data can beaccomplished in a variety of ways such as by receiving data as aparameter of a function call or a call to an application programminginterface. In some implementations, process of obtaining, acquiring,receiving, or inputting analog or digital data can be accomplished bytransferring data via a serial or parallel interface. In anotherimplementation, process of obtaining, acquiring, receiving, or inputtinganalog or digital data can be accomplished by transferring data via acomputer network from providing entity to acquiring entity. Referencesmay also be made to providing, outputting, transmitting, sending, orpresenting analog or digital data. In various examples, process ofproviding, outputting, transmitting, sending, or presenting analog ordigital data can be accomplished by transferring data as an input oroutput parameter of a function call, a parameter of an applicationprogramming interface or interprocess communication mechanism.

Although discussion above sets forth example implementations ofdescribed techniques, other architectures may be used to implementdescribed functionality, and are intended to be within scope of thisdisclosure. Furthermore, although specific distributions ofresponsibilities are defined above for purposes of discussion, variousfunctions and responsibilities might be distributed and divided indifferent ways, depending on circumstances.

Furthermore, although subject matter has been described in languagespecific to structural features and/or methodological acts, it is to beunderstood that subject matter claimed in appended claims is notnecessarily limited to specific features or acts described. Rather,specific features and acts are disclosed as exemplary forms ofimplementing the claims.

What is claimed is:
 1. A processor comprising: one or more circuits toperform an application programming interface (API) to indicate a maximumnumber of blocks of threads capable of being scheduled in parallel. 2.The processor of claim 1, wherein the maximum number is of a group ofblocks, the group being of multiple groups of blocks of threads of asoftware kernel.
 3. The processor of claim 1, wherein the maximum numberis of a group of blocks of multiple groups of blocks of a grid ofblocks.
 4. The processor of claim 1, wherein the maximum number ofblocks is based, at least in part, on an architecture of a graphicsprocessing unit (GPU).
 5. The processor of claim 1, wherein the maximumnumber of blocks is a limit of a number of allowable groups of blocks ofthreads of a software kernel.
 6. The processor of claim 1, wherein theAPI is to indicate the maximum number by returning the maximum number.7. The processor of claim 1, wherein the maximum number is based, atleast in part, on one or more properties of another processor.
 8. Theprocessor of claim 1, wherein the maximum number is a limit on a numberof partitions of blocks of threads of a group of threads.
 9. Theprocessor of claim 1, wherein the maximum number is a limit on a numberof blocks in a group of blocks, the group of blocks being one ofmultiple groups of blocks of a grid of blocks.
 10. Acomputer-implemented method comprising: performing an applicationprogramming interface (API) to indicate a maximum number of blocks ofthreads capable of being scheduled in parallel.
 11. Thecomputer-implemented method of claim 10, wherein the maximum number isof a group of blocks, the group being of multiple groups of blocks ofthreads of a software kernel.
 12. The computer-implemented method ofclaim 10, wherein the maximum number is of a group of blocks of multiplegroups of blocks of a grid of blocks.
 13. The computer-implementedmethod of claim 10, wherein the API the maximum number of blocks isbased, at least in part, on an architecture of a graphics processingunit (GPU).
 14. The computer-implemented method of claim 10, wherein themaximum number of blocks is a limit of a number of allowable groups ofblocks of threads of a software kernel.
 15. The computer-implementedmethod of claim 10, wherein the API is to indicate the maximum number byreturning the maximum number.
 16. The computer-implemented method ofclaim 10, wherein the maximum number is based, at least in part, on oneor more properties of a GPU.
 17. The computer-implemented method ofclaim 10, wherein the maximum number is a limit on a number ofpartitions of blocks of threads of a group of threads.
 18. Thecomputer-implemented method of claim 10, wherein the maximum number is alimit on a number of blocks in a group of blocks, the group of blocksbeing one of multiple groups of blocks of a grid of blocks.
 19. Acomputer system comprising: one or more processors and memory storingexecutable instructions that, if performed by the one or moreprocessors, are to perform an application programming interface (API) toindicate a maximum number of blocks of threads capable of beingscheduled in parallel.
 20. The computer system of claim 19, wherein themaximum number is of a group of blocks, the group being of multiplegroups of blocks of threads of a software kernel.
 21. The computersystem of claim 19, wherein the maximum number is of a group of blocksof multiple groups of blocks of a grid of blocks.
 22. The computersystem of claim 19, wherein the API the maximum number of blocks isbased, at least in part, on an architecture of a graphics processingunit (GPU).
 23. The computer system of claim 19, wherein the maximumnumber of blocks is a limit of a number of allowable groups of blocks ofthreads of a software kernel.
 24. The computer system of claim 19,wherein the API is to indicate the maximum number by returning themaximum number.
 25. The computer system of claim 19, wherein the maximumnumber is based, at least in part, on one or more properties of aprocessor of the one or more processors.
 26. The computer system ofclaim 19, wherein the maximum number is a limit on a number ofpartitions of blocks of threads of a group of threads.
 27. The computersystem of claim 19, wherein the maximum number is a limit on a number ofblocks in a group of blocks, the group of blocks being one of multiplegroups of blocks of a grid of blocks.
 28. A machine-readable mediumhaving stored thereon a set of instructions, which if performed by oneor more processors, are to perform an application programming interface(API) to indicate a maximum number of blocks of threads capable of beingscheduled in parallel.
 29. The machine-readable medium of claim 28,wherein the maximum number is of a group of blocks, the group being ofmultiple groups of blocks of threads of a software kernel.
 30. Themachine-readable medium of claim 28, wherein the maximum number is of agroup of blocks of multiple groups of blocks of a grid of blocks. 31.The machine-readable medium of claim 28, wherein the API the maximumnumber of blocks is based, at least in part, on an architecture of agraphics processing unit (GPU).
 32. The machine-readable medium of claim28, wherein the maximum number of blocks is a limit of a number ofallowable groups of blocks of threads of a software kernel.
 33. Themachine-readable medium of claim 28, wherein the API is to indicate themaximum number by returning the maximum number.
 34. The machine-readablemedium of claim 28, wherein the maximum number is based, at least inpart, on one or more properties of a processor of the one or moreprocessors.
 35. The machine-readable medium of claim 28, wherein themaximum number is a limit on a number of partitions of blocks of threadsof a group of threads.
 36. The machine-readable medium of claim 28,wherein the maximum number is a limit on a number of blocks in a groupof blocks, the group of blocks being one of multiple groups of blocks ofa grid of blocks.